Re: [Bug Fix]: Do 32-bit table calculations in pre-processor

[Michael S. Zick]

On Fri July 3 2009, H. Peter Anvin wrote:
> Michael S. Zick wrote:
> >>>
> >> The CPUID flags, in particular the pse flag.
> >>
> > 
> > I haven't touch anything that would have changed that -
> > so this should be representative (the *&^*% datasheet says yes to pse also)
> > 
> 
> Actually, come to think of it, we don't generate PSE page tables
> initially -- we only later go in and reclaim the page tables if we
> switch to PSE (and $DEITY knows if we're doing it correctly...)
>

I am of that age range where senility has to be considered, but not this time:

"Via C7-M Datasheet", May 2008 (supposed to be most recent) -

page 22 - section 2.3.7 - Table 2-14 "CR4 Bits"
"<5> PAE: Enables address extensions; C7-M:<r>" 
<quote>An "r" means that this bit is reserved.  It appears as a 0 when read,
and a GP exception is signaled if an attemp is made to write a 1 to this bit.</quote>

Same document -
page 16 - section 2.3.2 - Table 2-3 "CPUID Feature Flag Values (EAX=1)"
<EDX:6> PAE: Physical address extensions; C7:<1>

So take your pick - it might be there or it might not - - -
If you like that one, read the MCE bit "Documentation"  ;)

Note: When this bit is (attempted) to be set in head.S I think that the
GP fault is still "no-opted" by that dummy routine.
So we would never hear about it.
Also, according to H.W. the NX bit is a lie told to keep some OS's happy.

And then, of course, the silicon can have micro-code updates - -
All bets are off if mine works the same as yours does.  ;)

Mike
> 	-hpa
> 


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