[057/136] drm/i915: prevent FIFO calculation overflows on 32 bits with high dotclocks

[Greg KH]

2.6.31-stable review patch.  If anyone has any objections, please let us know.

------------------
From: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>

commit d660467c3ff2a0b7413e1b7a51452b34ffb49e5f upstream.

A very high dotclock (e.g. 229500kHz as reported by Anton) can cause
the entries_required variable to overflow, potentially leading to a
FIFO watermark value that's too low to support the given mode.  Split
the division across the calculation to avoid this.

Reported-by: Anton Khirnov <wyskas@xxxxxxxxx>
Tested-by: Anton Khirnov <wyskas@xxxxxxxxx>
Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>
Signed-off-by: Greg Kroah-Hartman <gregkh@xxxxxxx>

---
 drivers/gpu/drm/i915/intel_display.c |    9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -1858,7 +1858,14 @@ static unsigned long intel_calculate_wm(
 {
 	long entries_required, wm_size;
 
-	entries_required = (clock_in_khz * pixel_size * latency_ns) / 1000000;
+	/*
+	 * Note: we need to make sure we don't overflow for various clock &
+	 * latency values.
+	 * clocks go from a few thousand to several hundred thousand.
+	 * latency is usually a few thousand
+	 */
+	entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
+		1000;
 	entries_required /= wm->cacheline_size;
 
 	DRM_DEBUG("FIFO entries required for mode: %d\n", entries_required);


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