Re: [PATCH] pci: overwite pci bridge res regs to get big range

[Jesse Barnes]

On Sun, 13 Sep 2009 15:57:10 -0700
Yinghai Lu <yinghai@xxxxxxxxxx> wrote:

> 
> 
> found one system:
> [   71.120590] pci 0000:40:05.0: scanning behind bridge, config
> 4f4a40, pass 0 [   71.138283] PCI: Scanning bus 0000:4a
> [   71.140341] pci 0000:4a:00.0: found [15b3:6278] class 000c06
> header type 00 [   71.157173] pci 0000:4a:00.0: reg 10 64bit mmio:
> [0x000000-0x0fffff] [   71.161697] pci 0000:4a:00.0: reg 18 64bit
> mmio pref: [0x000000-0x7fffff] [   71.179403] pci 0000:4a:00.0: reg
> 20 64bit mmio pref: [0x000000-0xfffffff] [   71.185366] pci
> 0000:4a:00.0: calling quirk_resource_alignment+0x0/0x1dd
> [   71.200846] pci 0000:4a:00.0: disabling ASPM on pre-1.1 PCIe
> device.  You can enable it with 'pcie_aspm=force' [   71.219623] PCI:
> Fixups for bus 0000:4a [   71.222194] pci 0000:40:05.0: bridge 32bit
> mmio: [0xcf000000-0xcf0fffff] [   71.238662] pci 0000:40:05.0: bridge
> 64bit mmio pref: [0xcd800000-0xcdffffff] [   71.255793] PCI: Bus scan
> for 0000:4a returning with max=4a

Applied to my for-linus branch, thanks Yinghai.

-- 
Jesse Barnes, Intel Open Source Technology Center
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