Re: [patch 2/2] x86, irq: use 0x20 for the IRQ_MOVE_CLEANUP_VECTORinstead of 0x1f

[H. Peter Anvin]

On 02/01/2010 01:24 PM, Suresh Siddha wrote:
> 
> As we are using the code from 2.6.28 and no one noticed/complained about
> this issue for more than 1.5 years, probably the pentium APIC issue is
> not wide-spread.
> 

I *think* it's applicable to all CPUs Pentium III or earlier (but not
Pentium 4 -- I'm unsure about the Pentium M.)  I don't know about
non-Intel CPUs; I have a vague memory of the Transmeta Efficeon (the
only Transmeta chip with an APIC) *not* having this limitation.

The exact reference is SDM vol 3A 10.8.4, page 10-41 [rev 033US Dec 2009]:

For the P6 family and Pentium processors, the IRR and ISR registers can
queue no more than two interrupts per priority level, and will reject
other interrupts that are received within the same priority level.

However, section 10.8.2 bullet 3 on page 10-38 (and the flowchart on
page 10-37) indicate that such an interrupt is returned to the IOAPIC
for a later retry, i.e. it's not lost.  As such, it's not clear to me
from reading the SDM that there is actually a problem here...

	-hpa
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/