Re: [PATCH 3/5] perf, x86: Disable PEBS on clowertown chips

[Peter Zijlstra]

On Fri, 2010-03-05 at 11:28 -0800, Stephane Eranian wrote:
> On Fri, Mar 5, 2010 at 11:15 AM, Peter Zijlstra <peterz@xxxxxxxxxxxxx> wrote:
> > On Fri, 2010-03-05 at 10:58 -0800, Stephane Eranian wrote:
> >> >        case 15: /* original 65 nm celeron/pentium/core2/xeon, "Merom"/"Conroe" */
> >> > +               x86_pmu.quirks = intel_clowertown_quirks;
> >>
> >> That's too coarse grain!
> >> It is more subtle than this. Some of the errata are marked as Plan
> >> fix. They seem to be
> >> fixed in later models. Your looking at the E5xxx series errata but the
> >> E7xxx do not have
> >> the same problems.
> >
> > OK, I'll look at those errata again and try to come up with a stepping
> > test for this errata.
> >
> There is erratum which you need to implement the workaround for and
> this is AAJ91 on Nehalem. It does happen.

Yes, I found that one too today. Its on my todo list.

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