Re: [RFC PATCH] Update the cachetlb.txt file WRT flush_dcache_pageand update_mmu_cache

[FUJITA Tomonori]

On Mon, 10 May 2010 11:16:47 +0100
Catalin Marinas <catalin.marinas@xxxxxxx> wrote:

> > I don't think that just replacing sparc64 with IA64 helps much here
> > since we still have the problem that the whole cache handling
> > (architectures, subsystems, file systems) is inconsistent. I think
> > that we need to agree on it first.
> 
> Yes, this need to be agreed and hopefully this thread is a starting
> point for such discussion.

Hopefully, but I'm not sure what we need to agree is clear enough.

If we invert the meaning of PG_arch_1 (from PG_dcache_dirty to
PG_dcache_clean) like the way IA64 and POWERPC to use the bit to solve
I/D coherency, we can avoid calling flush_dcache_page() at low level
drivers or their subsystems (ide_* macros, libata,
bio_flush_dcache_pages, rq_flush_dcache_pages, etc). Architectures
that need to handle D aliasing and I/D coherence need two bits
respectively (needs another PG_arch_2 bit) to do flushes effectively.

Right?
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