Re: [LKML] Re: [PATCH v3] ad7877: keep dma rx buffers in seperate cache lines

[FUJITA Tomonori]

On Wed, 12 May 2010 00:35:45 -0400
Mike Frysinger <vapier.adi@xxxxxxxxx> wrote:

> On Tue, May 11, 2010 at 23:23, FUJITA Tomonori wrote:
> > Seems that kmalloc is not cacheline aligned on some architectures but
> > they works. Probably, we might be just lucky because in general they
> > allocate larger buffers than 64 for DMA via kmalloc and the buffers
> > are aligned on the size?
> 
> i think the magic combo is:
>  - DMA buffer is written to (receive)
>  - some driver state is in the same cacheline as the DMA buffer
>  - that driver state is used after the flush but before the DMA finishes
>  - only on arches that need software cache coherency
> 
> so i could see this not being an obvious issue for many people

Yeah, we don't hit such condition everyday. And as I said, SCSI
usually uses kmalloc'ed buffers rather than the cache size (buffers
are aligned on roundup_pow_of_two(the allocated size)). But I think
that we want to fix this issue explicitly. I guess that it would be
better to start a new thread about this issue.
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