[tip:perf/urgent] perf_events: Fix Intel Westmere event constraints

From: tip-bot for Stephane Eranian
Date: Thu Jun 10 2010 - 08:25:43 EST


Commit-ID: d11007703c31db534674ebeeb9eb047bbbe758bd
Gitweb: http://git.kernel.org/tip/d11007703c31db534674ebeeb9eb047bbbe758bd
Author: Stephane Eranian <eranian@xxxxxxxxxx>
AuthorDate: Thu, 10 Jun 2010 13:25:01 +0200
Committer: Ingo Molnar <mingo@xxxxxxx>
CommitDate: Thu, 10 Jun 2010 14:16:32 +0200

perf_events: Fix Intel Westmere event constraints

Based on Intel Vol3b (March 2010), the event
SNOOPQ_REQUEST_OUTSTANDING is restricted to counters 0,1 so
update the event table for Intel Westmere accordingly.

Signed-off-by: Stephane Eranian <eranian@xxxxxxxxxx>
Cc: peterz@xxxxxxxxxxxxx
Cc: paulus@xxxxxxxxx
Cc: davem@xxxxxxxxxxxxx
Cc: fweisbec@xxxxxxxxx
Cc: perfmon2-devel@xxxxxxxxxxxx
Cc: eranian@xxxxxxxxx
Cc: <stable@xxxxxxxxxx> # .34.x
LKML-Reference: <4c10cb56.5120e30a.2eb4.ffffc3de@xxxxxxxxxxxxx>
Signed-off-by: Ingo Molnar <mingo@xxxxxxx>
---
arch/x86/kernel/cpu/perf_event_intel.c | 1 +
1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
index fdbc652..214ac86 100644
--- a/arch/x86/kernel/cpu/perf_event_intel.c
+++ b/arch/x86/kernel/cpu/perf_event_intel.c
@@ -72,6 +72,7 @@ static struct event_constraint intel_westmere_event_constraints[] =
INTEL_EVENT_CONSTRAINT(0x51, 0x3), /* L1D */
INTEL_EVENT_CONSTRAINT(0x60, 0x1), /* OFFCORE_REQUESTS_OUTSTANDING */
INTEL_EVENT_CONSTRAINT(0x63, 0x3), /* CACHE_LOCK_CYCLES */
+ INTEL_EVENT_CONSTRAINT(0xb3, 0x1), /* SNOOPQ_REQUEST_OUTSTANDING */
EVENT_CONSTRAINT_END
};

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