Re: [PATCH -v2] x86, pci: Handle fallout pci devices with peer rootbus

[Yinghai Lu]

On 06/14/2010 11:14 AM, Jesse Barnes wrote:
> On Mon, 14 Jun 2010 10:47:59 -0700
> Yinghai Lu <yinghai.lu@xxxxxxxxxx> wrote:
> 
>>
>> Graham bisected
>> |    commit 3e3da00c01d050307e753fb7b3e84aefc16da0d0
>> |    x86/pci: AMD one chain system to use pci read out res
>>
>> cause the SND_HDA_INTEL doesn't work anymore.
>>
>> https://bugzilla.kernel.org/show_bug.cgi?id=16007
>>
>> It turns out that his system with via chipset only have one hypertransport
>> chain, but does have one extra orphan device 80:01.0
>>
>>  PCI: Probing PCI hardware (bus 00)
>>  PCI: Discovered primary peer bus 80 [IRQ]
>>
>>  node 0 link 0: io port [1000, ffffff]
>>  TOM: 0000000080000000 aka 2048M
>>  node 0 link 0: mmio [e0000000, efffffff]
>>  node 0 link 0: mmio [a0000, bffff]
>>  node 0 link 0: mmio [80000000, ffffffff]
>>  bus: [00, ff] on node 0 link 0
>>
>> Try to make peer root buses to share same mmio/io resources if those peer root
>> buses fall into the same bus range.
>>
>> Also need to update insert_resource to avoid insert same resource two times.
> 
> So 3e3da00c01d050307e753fb7b3e84aefc16da0d0 was supposed to address the
> case where some laptop RAM ranges ended up incorrect.  Would using _CRS
> on those machines also address that problem?  If so, we should consider
> dropping amd_bus.c like we did with intel_bus.c.
> 
> Yinghai, do you still have people from the RAM bug that could test
> using _CRS data?

I can not find the mail anymore.

looks like someone is using one AMD k8 Aruma laptop for firewire development.

YH
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