Avi Kivity wrote:
On 07/02/2010 11:00 AM, Xiao Guangrong wrote:The iosapic also using 32-bit to access registers:
The IOAPIC spec says:The ioapic code also implements the ia64 iosapic. I'm guessing that
When accessing these registers, accesses must be done one dword at a
time.
For example, software should never access byte 2 from the Data
register before
accessing bytes 0 and 1. The hardware will not attempt to recover from
a bad
programming model in this case.
So, this patch removes other width access
does support 64-bit accesses. Please check the iosapic documentation.
All registers are accessed using 32-bit uncacheable loads and stores to a reserved memory location
in system memory. This implies that to modify a field (e.g., a bit or a byte) in any register, the
whole 32-bit register must be read, the field modified, and the 32 bits written back. Partial register
access, or non-aligned register access, are implementation-defined by the I/O xAPIC and will not
be compatible across different implementations. Also, registers that are described as 64 bits wide
are accessed as multiple independent 32-bit registers.
[ From<< Intel Itanium Processor Family Interrupt Architecture Guide>>, P2-6 ]
There might be guests that use incorrect access despite theIf the OS contravene the spec, i thinks it's the OS's bug, also, i have tested some versions
documentation; if real hardware supports it, it should work. So we need
to start with just a warning, and allow the access. Later we can drop
the invalid access.
windows/linux guests, it's no broken, can we directly drop the other wide access?