On 07/13/10 15:15, Zachary Amsden wrote:
What about across processor sockets? Aren't CPUs brought up at differentWhat prevents a vcpu from seeing its TSC go backwards, in case the firstNothing, unfortunately. However, the TSC would already have to be out
write in the 5 second window is smaller than the victim vcpu's last
visible TSC value ?
of sync in order for the problem to occur. It can never happen in
normal circumstances on a stable hardware TSC except in one case;
migration. During the CPU state transfer phase of migration, however,
points such that their TSCs start at different times?