Re: [patch 1/2] x86_64 page fault NMI-safe
From: Maciej W. Rozycki
Date: Wed Jul 14 2010 - 17:45:23 EST
On Wed, 14 Jul 2010, Linus Torvalds wrote:
> No. As mentioned, there is no such counter in real hardware either.
There is a 1-bit counter or actually a latch.
> Look at what happens for the not-nested case:
>
> - NMI1 triggers. The CPU takes a fault, and runs the NMI handler with
> NMI's disabled
Correct.
> - NMI2 triggers. Nothing happens, the NMI's are disabled.
The NMI latch records the second NMI. Note this is edge-sensitive like
the NMI line itself.
> - NMI3 triggers. Again, nothing happens, the NMI's are still disabled
Correct.
> - the NMI handler returns.
>
> - What happens now?
NMI2 latched above causes the NMI handler to be invoked as the next
instruction after IRET. The latch is cleared as the interrupt is taken.
> How many NMI interrupts do you get? ONE. Exactly like my "emulate it
> in software" approach. The hardware doesn't have any counters for
> pending NMI's either. Why should the software emulation have them?
Two. :)
Maciej
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