Re: [now bisected] i915: 2.6.36-rc2 hoses my Intel display

[Chris Wilson]

On Tue, 24 Aug 2010 07:16:26 -0600, Jonathan Corbet <corbet@xxxxxxx> wrote:
> On Tue, 24 Aug 2010 00:55:54 +0100
> Chris Wilson <chris@xxxxxxxxxxxxxxxxxx> wrote:
> 
> > In threes. Hmm, one for primary, cursor and self-refresh. drm.debug=0xe
> > would be interesting to see what the pixel clock is.
> > 
> > Can you grab one before the bad commit and one after? If there is a change
> > that may help pin-point the mistake. Or indicate further problems...
> 
> OK, three files attached; drm.good is from 2.6.35, drm.bad is from
> 2.6.36-rc2.  I also stripped the times and did a diff, in case that's
> useful.

[snip]

> -[drm:intel_calculate_wm], FIFO entries required for mode: 48
> -[drm:intel_calculate_wm], FIFO watermark level: -22
> +[drm:intel_calculate_wm], FIFO entries required for mode: 49
> +[drm:intel_calculate_wm], FIFO watermark level: -23
> +*ERROR* Insufficient FIFO for plane, expect flickering: entries required = 51, available = 28.
>  [drm:intel_calculate_wm], FIFO entries required for mode: 0
>  [drm:intel_calculate_wm], FIFO watermark level: 29
>  [drm:i9xx_update_wm], FIFO watermarks - A: 1, B: 29
> -[drm:i9xx_update_wm], self-refresh entries: 60
> -[drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 35
> -[drm:i915_get_vblank_counter], trying to get vblank count for disabled pipe 1
> +[drm:i9xx_update_wm], self-refresh entries: 120
> +[drm:i9xx_update_wm], Setting FIFO watermarks - A: 1, B: 29, C: 2, SR 1

I'm going to focus on this since this could account for the on-screen
corruption. Here we suddenly double the computed minimal FIFO size for
self-refresh and due to a separate bug program a minimal low watermark.

That should addressed with
http://cgit.freedesktop.org/~ickle/linux-2.6/commit/?h=drm-testing&id=30c127264ef9729bcef1d9901718f9a8a47be6a4
however that patch isn't quite ready yet since Jesse pointed out that
some chipsets do indeed want a high-watermark instead of the low-watermark
used, at least, for gen3+.

The question though is why that bad commit would cause a doubling of the
SR. Thanks for the diff, I now know that I need to look more closely at
the mode-fixup for SDVO.

-- 
Chris Wilson, Intel Open Source Technology Centre
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