Re: [tip:perf/urgent] perf, x86: Catch spurious interrupts afterdisabling counters

[Stephane Eranian]

On Wed, Sep 29, 2010 at 3:56 PM, Stephane Eranian <eranian@xxxxxxxxxx> wrote:
> On Wed, Sep 29, 2010 at 3:39 PM, Robert Richter <robert.richter@xxxxxxx> wrote:
>> On 29.09.10 09:13:30, Stephane Eranian wrote:
>>
>>> for_each_set_bit(bit, (unsigned long *)&status, X86_PMC_IDX_MAX) {
>>> Â Â Â Â Â Â Â Â struct perf_event *event = cpuc->events[bit];
>>>
>>> Â Â Â Â Â Â Â Â handled++;
>>>
>>> Â Â Â Â Â Â Â Â if (!test_bit(bit, cpuc->active_mask))
>>
>> Â Â Â Â Â Â Â Â Â Â Â Â/* spurious interrupt here */
>>
>>> Â Â Â Â Â Â Â Â Â Â continue;
>>> }
>>>
>>> I think the logic is similar. What makes the difference, it seems, is that
>>> handled is incremented unconditionally if the ovfl_mask says it has
>>> an overflow, i.e., before active_mask is checked.
>>
>> Note that we can use here for_each_set_bit() since we have the status
>> mask. So we may increment handled always.
>>
>> On AMD we use for_each_counter(), but only check active counters to
>> avoid unnecessary rdmsrl()s for unused counters. But here, we only can
>> increment handled if we detect an overflow or if we know a counter was
>> disabled.
>>
>>> On Westmere, we've seen situations where the overflow mask and active
>>> mask did not agree.
>>
>> It's the 'spurious interrupt' branch above.
>>
>>> On counter disable, the overflow mask bit is not cleared, thus one may iterate
>>> in the loop and fail the active_mask. But handled would be incremented in that
>>> case, so that would behave like in your patch.
>>
>> Right, spurious interrupts are counted and a 'handled' is returned.
>>
> Ok, I think we agree on this. It is handled in the Intel case, though it
> is not clearly explained with a comment.
> The P4 case needs to be fixed.
>
> Here is another difference I noticed in x86_handle_irq() vs.
> intel_pmu_handle_irq().
> For Intel, handled is incremented even if there is no 64-bit overflow.
>
> With generic X86, it is incremented only when you have a 64-bit
> overflow. I think that's wrong. You don't hit that condition very often
> on AMD because counters are 47 bits wide, but this is generic code
> and on P6 you definitively will. I believe you need to hoist handled++
> just after the check on active_mask.
>
>
> What do you think?
>
In other words, I think handled is there to track interrupts, i.e., hw
counter overflows, and not 64-bit software counter overflows (which
do trigger sample recording).
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