Re: [RFC PATCH 2/3 v2] perf: Implement Nehalem uncore pmu

[Stephane Eranian]

On Wed, Dec 1, 2010 at 4:21 AM, Lin Ming <ming.m.lin@xxxxxxxxx> wrote:
>
> On Fri, 2010-11-26 at 18:06 +0800, Stephane Eranian wrote:
> > On Fri, Nov 26, 2010 at 10:00 AM, Lin Ming <lin@xxxxxxx> wrote:
> > > On Fri, Nov 26, 2010 at 4:33 PM, Stephane Eranian <eranian@xxxxxxxxxx> wrote:
> > >> Lin,
> > >>
> > >> Looked at the perfmon code, and it seems the mask is actual
> > >> cores, not threads:
> > >> Â Â Â Â Â Â Â Ârdmsrl(MSR_NHM_UNC_GLOBAL_CTRL, val);
> > >> Â Â Â Â Â Â Â Âval |= 1ULL << (48 + cpu_data(smp_processor_id()).cpu_core_id);
> > >> Â Â Â Â Â Â Â Âwrmsrl(MSR_NHM_UNC_GLOBAL_CTRL, val);
> > >>
> > >> That seems to imply both threads will get the interrupt.
> > >>
> > >> In the the overflowed event was programmed from on of the two threads, that
> > >> means one will process the overflow, the other will get spurious.
> > >>
> > >> On the cores where no uncore was programmed, then both threads will have
> > >> a spurious interrupt.
> > >
> > > But in my test, if HT is on, only the 2 theads in one of the four cores
> > > will receive the interrupt. Even worse, we don't know which core will
> > > receive the interrupt
> > > when overflow happens.
> > >
> > The MSR_NHM_UNC_GLOBAL_CTRL is per socket not per core.
>
> Understood.
>
> >
> > > I'll do more tests to verify this.
> >
> > In your tests, are your programming the same uncore event
> > across all CPUs? If so then you may have a race condition
> > setting the MSR because it read-modify-write.
> >
> > What about you program only one uncore event from one CPU?
>
> This is what I tested, programming only one uncore event from one CPU.

> When HT is off, all four cores in the socket receive the interrupt.

If the value of the MSR is 0xf << 48?

> When HT is on, only the 2 threads in one of the four cores receive the
> interrupt.
Something is not right here. Next week, I may be able to run some tests
on a Nehalem using perfmon to compare. Could you also send me your
latest uncore patch against tip-x86?
Thanks.
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