Re: JRCU Theory of Operation

[Joe Korty]

On Sun, Mar 13, 2011 at 12:56:27AM -0500, Paul E. McKenney wrote:
> > Even though I keep saying 50msecs for everything, I
> > suspect that the Q switching meets all the above quiescent
> > requirements in a few tens of microseconds.  Thus even
> > a 1 msec JRCU sampling period is expected to be safe,
> > at least in regard to Q switching.
> 
> I would feel better about this is the CPU vendors were willing to give
> an upper bound...

I suspect they don't because they don't really know
themselves .. in that whatever it is, it keeps changing
from chip to chip, trying to describe such would be beyond
the english language, and any description would tie them
down on what they could do in future chip designs.

But, there is a hint in current behavior.  It is well known
that many multithreaded apps don't uses barriers at all;
the authors had no idea what they are for.  Yet such apps
largely work.  This implies that the chip designers are
very aggressive in doing implied memory barriers wherever
possible, and they are very aggressive in pushing out
stores to caches very quickly even when memory barriers,
implied or not, are not present.

Joe
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