Re: [PATCH -tip] perf, x86: P4 PMU - Add missing read of a counterbefore test

[Cyrill Gorcunov]

On 03/24/2011 11:48 AM, Ingo Molnar wrote:
> 
> * Cyrill Gorcunov <gorcunov@xxxxxxxxx> wrote:
> 
>> Don, I've added yours SOB, ok? (The patch is attached to avoid
>> space/tabs problem
>> due to web-mail client)
> 
> The patch lacks a proper description about the motivation and effects of the 
> patch.
> 
> Thanks,
> 
> 	Ingo

Ingo, does this one looks better?

---
From: Don Zickus <dzickus@xxxxxxxxxx>
Subject: [PATCH -tip] perf, x86: P4 PMU - Add missing read of MSR register to catch unflagged overflows

The read of a proper MSR register was missed so instead of a counter the
configration register is tested (it has ARCH_P4_UNFLAGGED_BIT always
cleared) and unflagged overflows never have been catched. Fix it by
reading a proper MSR register.

Signed-off-by: Don Zickus <dzickus@xxxxxxxxxx>
Signed-off-by: Cyrill Gorcunov <gorcunov@xxxxxxxxxx>
---
 arch/x86/kernel/cpu/perf_event_p4.c |    1 +
 1 file changed, 1 insertion(+)

Index: linux-2.6.tip/arch/x86/kernel/cpu/perf_event_p4.c
===================================================================
--- linux-2.6.tip.orig/arch/x86/kernel/cpu/perf_event_p4.c
+++ linux-2.6.tip/arch/x86/kernel/cpu/perf_event_p4.c
@@ -777,6 +777,7 @@ static inline int p4_pmu_clear_cccr_ovf(
 	 * the counter has reached zero value and continued counting before
 	 * real NMI signal was received:
 	 */
+	rdmsrl(hwc->event_base, v);
 	if (!(v & ARCH_P4_UNFLAGGED_BIT))
 		return 1;


-- 
    Cyrill
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