Re: advice sought: practicality of SMP cache coherency implemented inassembler (and a hardware detect line)

[Will Newton]

On Fri, Mar 25, 2011 at 9:52 PM, Luke Kenneth Casson Leighton
<luke.leighton@xxxxxxxxx> wrote:
> so, bearing in mind that sensible answers will likely result in offers
> of a consulting contract to actually *implement* the software /
> assembly code for the linux kernel modifications required (yes, linux
> is already available for this RISC processor type - but only in
> single-core), i would greatly appreciate some help in getting answers
> to these questions:
>
> * is this even a good idea? does it "fly"?

Probably not. Is it a virtual or physical indexed cache? Do you have a
precise workload in mind? If you have a very precise workload and you
don't expect to get many write conflicts then it could be made to
work.

> * if it does work, at what point do the number of cores involved just
> make it... completely impractical?  over 2?  over 4?  8? 16?

You would have to simulate it with your workload to know the answer to
that, but if you're pushing to higher number of cores I think it would
pay to do this properly.

> occurred back in 2005 or so - this multi-core processor is going to be
> based around an existing proven 20-year-old well-established RISC core
> that has been running linux for over a decade, it just has never been
> put into an SMP arrangement before and we're on rather short
> timescales to get it done.

There are a number of mature cores out there that can do this already
and can be bought off the shelf, I wouldn't underestimate the
difficulty of getting your cache coherency protocol right particularly
on a limited time/resource budget.
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@xxxxxxxxxxxxxxx
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/