Re: [PATCH v3] ata: pata_at91.c bugfix for high master clock

From: Igor Plyatov
Date: Mon Mar 28 2011 - 09:04:39 EST


Hi!

Please abandon this patch and use its new version 4 with subjects:
* "[PATCH v4 1/2] ata: pata_at91.c bugfix for initial_timing
initialisation"
* "[PATCH v4 2/2] ata: pata_at91.c bugfix for high master clock"

Best regards!
--
Igor Plyatov

> The AT91SAM9 microcontrollers with master clock higher then 105 MHz
> and PIO0, have overflow of the NCS_RD_PULSE value in the MSB. This
> lead to "NCS_RD_PULSE" pulse longer then "NRD_CYCLE" pulse and driver
> does not detect ATA device.
>
> Signed-off-by: Igor Plyatov <plyatov@xxxxxxxxx>
> ---
> drivers/ata/pata_at91.c | 8 +++++++-
> 1 files changed, 7 insertions(+), 1 deletions(-)
>
> diff --git a/drivers/ata/pata_at91.c b/drivers/ata/pata_at91.c
> index d1aaeb5..3c2bf86 100644
> --- a/drivers/ata/pata_at91.c
> +++ b/drivers/ata/pata_at91.c
> @@ -33,11 +33,12 @@
>
>
> #define DRV_NAME "pata_at91"
> -#define DRV_VERSION "0.1"
> +#define DRV_VERSION "0.2"
>
> #define CF_IDE_OFFSET 0x00c00000
> #define CF_ALT_IDE_OFFSET 0x00e00000
> #define CF_IDE_RES_SIZE 0x08
> +#define NCS_RD_PULSE_LIMIT 0x3f /* maximal value for pulse bitfields */
>
> struct at91_ide_info {
> unsigned long mode;
> @@ -110,6 +111,11 @@ static void set_smc_timing(struct device *dev,
> /* (CS0, CS1, DIR, OE) <= (CFCE1, CFCE2, CFRNW, NCSX) timings */
> ncs_read_setup = 1;
> ncs_read_pulse = read_cycle - 2;
> + if (ncs_read_pulse > NCS_RD_PULSE_LIMIT) {
> + ncs_read_pulse = NCS_RD_PULSE_LIMIT;
> + dev_warn(dev, "ncs_read_pulse limited to maximal value %lu\n",
> + ncs_read_pulse);
> + }
>
> /* Write timings same as read timings */
> write_cycle = read_cycle;


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