Re: [regression 2.6.39-rc2][bisected] "perf, x86: P4 PMU - Readproper MSR register to catch" and NMIs

[Ingo Molnar]

* Cyrill Gorcunov <gorcunov@xxxxxxxxxx> wrote:

> -	apic_write(APIC_LVTPC, APIC_DM_NMI);
> 
>  	handled = x86_pmu.handle_irq(args->regs);
>  	if (!handled)
>  		return NOTIFY_DONE;
> 
> +	/*
> +	 * Unmasking should be done after IRQ handled, otherwise
> +	 * there is a race between clearing of counter overflow
> +	 * flag and LTV entry unmasking (which might lead to double
> +	 * NMIs generation).
> +	 */
> +	apic_write(APIC_LVTPC, APIC_DM_NMI);

Here we could leak a masked IRQ through the !handled path. If we got a LVTPC 
irq we better handle it and unmask the LVTPC unconditionally - regardless of 
whether we consider it 'handled' or not from the kernel POV ...

Thanks,

	Ingo
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