[tip:x86/cpu] x86, cpu: Fix detection of Celeron Covington stepping A1 and B0

[tip-bot for Ondrej Zary]

Commit-ID:  865be7a81071a77014c83cd01536c989eed362b4
Gitweb:     http://git.kernel.org/tip/865be7a81071a77014c83cd01536c989eed362b4
Author:     Ondrej Zary <linux@xxxxxxxxxxxxxxxxxxxx>
AuthorDate: Mon, 16 May 2011 21:38:08 +0200
Committer:  H. Peter Anvin <hpa@xxxxxxxxxxxxxxx>
CommitDate: Mon, 16 May 2011 13:24:21 -0700

x86, cpu: Fix detection of Celeron Covington stepping A1 and B0

Steppings A1 and B0 of Celeron Covington are currently misdetected as
Pentium II (Dixon). Fix it by removing the stepping check.

[ hpa: this fixes this specific bug... the CPUID documentation
  specifies that the L2 cache size can disambiguate additional CPUs;
  this patch does not fix that. ]

Signed-off-by: Ondrej Zary <linux@xxxxxxxxxxxxxxxxxxxx>
Link: http://lkml.kernel.org/r/201105162138.15416.linux@xxxxxxxxxxxxxxxxxxxx
Signed-off-by: H. Peter Anvin <hpa@xxxxxxxxxxxxxxx>
---
 arch/x86/kernel/cpu/intel.c |   10 ++++------
 1 files changed, 4 insertions(+), 6 deletions(-)

diff --git a/arch/x86/kernel/cpu/intel.c b/arch/x86/kernel/cpu/intel.c
index df86bc8..32e86aa 100644
--- a/arch/x86/kernel/cpu/intel.c
+++ b/arch/x86/kernel/cpu/intel.c
@@ -400,12 +400,10 @@ static void __cpuinit init_intel(struct cpuinfo_x86 *c)
 
 		switch (c->x86_model) {
 		case 5:
-			if (c->x86_mask == 0) {
-				if (l2 == 0)
-					p = "Celeron (Covington)";
-				else if (l2 == 256)
-					p = "Mobile Pentium II (Dixon)";
-			}
+			if (l2 == 0)
+				p = "Celeron (Covington)";
+			else if (l2 == 256)
+				p = "Mobile Pentium II (Dixon)";
 			break;
 
 		case 6:
--
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