Re: PCI BAR1 Unassigned

[Xianghua Xiao]

On Thu, May 19, 2011 at 3:27 PM, Jan Zwiegers <jan@xxxxxxxxxxxxxxxxxxxx> wrote:
> On 2011-05-19 08:50 PM, Bjorn Helgaas wrote:
>>
>> On Thu, May 19, 2011 at 10:28 AM, Jan Zwiegers<jan@xxxxxxxxxxxxxxxxxxxx>
>> Âwrote:
>>>
>>> I have the problem below where my PCI card's second BAR does not get
>>> assigned.
>>> What can be the cause of this problem?
>>> The last kernel I tested on which worked OK was 2.6.27.
>>> My current problematic kernel 2.6.35.
>>>
>>> 05:01.0 Unassigned class [ff00]: Eagle Technology PCI-703 Analog I/O Card
>>> (rev 5c)
>>> Â ÂFlags: bus master, slow devsel, latency 32, IRQ 22
>>> Â ÂMemory at 93b00000 (type 3, prefetchable) [size=2K]
>>> Â ÂMemory at<unassigned> Â(type 3, prefetchable)
>>> Â ÂCapabilities: [80] #00 [0600]
>>> Â ÂKernel modules: pci703drv
>>
>> Could be resource exhaustion or, more likely, we ran out because we
>> now assign resource to things that don't need them, leaving none for
>> things that *do* need them. ÂThis sounds like a regression, so we
>> should open a bugzilla for it and attach dmesg logs from 2.6.27 and
>> 2.6.35.
>>
>> Does this problem keep the driver from working? Â(Sometimes drivers
>> don't actually use all the BARs a device supports.)
>>
>> Bjorn
>>
>
> I'm the maintainer of the driver and was involved in the development of the
> board as well in 2003. The board uses two BARS and the second BAR is the
> most important. The board worked fine since the 2.4 days and only recently
> became problematic. I suspect it works on even later kernels than 27, maybe
> 2.6.32.
>
> My knowledge is too little to actually determine if the problem is because
> the FPGA based PCI interface is not within spec or something that changed in
> the kernel, because of the post .30 releases becoming more strict to PCI
> specification, i.e. BIOS / Kernel interaction.
>
> Jan
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What's the size for BAR1? one reason is that no more space to
align/allocate BAR1.

If the board stays the same then your FPGA might be the cause, I have
seen similar issues and they ended up in FPGA implementation.
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