On Thu, Jun 23, 2011 at 6:42 PM, David Daney<david.daney@xxxxxxxxxx> wrote:From: David Daney<ddaney@xxxxxxxxxxxxxxxxxx>
Signed-off-by: David Daney<ddaney@xxxxxxxxxxxxxxxxxx>
---
This is a revision of my main device-tree definitions from my previous
RFC. I wanted to get feedback on my changes to several bindings
before I set them in stone.
The changes are to bootbus.txt, compact-flash.txt and dma-engine.txt.
Basically there are a ton of parameters needed to initialize the boot
bus, and I just stuck them all in there. Is this the best way to
handle something like this?
I look forward to hearing any feedback.
Mostly looks good. Comments below.
g.
Thanks,
David Daney
.../devicetree/bindings/mips/cavium/bootbus.txt | 114 +++++
.../devicetree/bindings/mips/cavium/ciu.txt | 26 ++
.../bindings/mips/cavium/compact-flash.txt | 31 ++
.../devicetree/bindings/mips/cavium/dma-engine.txt | 21 +
.../devicetree/bindings/mips/cavium/gpio.txt | 48 ++
should be .../bindings/gpio/cavium.txt
.../devicetree/bindings/mips/cavium/mdio.txt | 27 ++
.../bindings/net/mdio.txt
and so on.
[...].../devicetree/bindings/mips/cavium/mix.txt | 40 ++
.../devicetree/bindings/mips/cavium/pip.txt | 98 +++++
.../devicetree/bindings/mips/cavium/twsi.txt | 34 ++
.../devicetree/bindings/mips/cavium/uart.txt | 19 +
.../devicetree/bindings/mips/cavium/uctl.txt | 47 ++
diff --git a/Documentation/devicetree/bindings/mips/cavium/bootbus.txt b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
new file mode 100644
index 0000000..2960ba8
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/bootbus.txt
@@ -0,0 +1,114 @@
+* Boot Bus
+
+The Octeon Boot Bus is a configurable parallel bus with 8 chip
+selects. Each chip select is independently configurable.
+
+Properties:
+- compatible: "cavium,octeon-3860-bootbus"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the Boot Bus' register bank.
+
+- #address-cells: Must be<2>. The first cell is the chip select
+ within the bootbus. The second cell is the offset from the chip select.
+
+- #size-cells: Must be<1>.
+
+- ranges: There must be one one triplet of (child-bus-address,
+ parent-bus-address, length) for each active chip select. If the
+ length element for any triplet is zero, the chip select is disabled,
+ making it inactive.
You don't need to actually define standard properties like 'ranges'.
You can save some text that way.
+
+- t-adr: An array of 8 elements specifying the ADR timing parameter
+ (in nS) for the each of the 8 chip selects.
Using arrays like this is a little awkward. Particularly if board
code needs to modify only one CS configuration; it then needs to
replace /all/ of the configuration values because there is no way for
DTC to modify a portion of property data. You may want to consider a
set of CS configuration child nodes with the parameters as properties.
Also, these property names are pretty terse. They should probably
carry a "cavium," prefix, and you can use longer names.
diff --git a/Documentation/devicetree/bindings/mips/cavium/ciu.txt b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
new file mode 100644
index 0000000..c8ff212
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/ciu.txt
@@ -0,0 +1,26 @@
+* Central Interrupt Unit
+
+Properties:
+- compatible: "cavium,octeon-3860-ciu"
+
+ Compatibility with all cn3XXX, cn5XXX and cn63XX SOCs.
+
+- interrupt-controller: This is an interrupt controller.
+
+- reg: The base address of the CIU's register bank.
+
+- #interrupt-cells: Must be<2>. The first cell is the bank within
+ the CIU and may have a value of 0 or 1. The second cell is the bit
+ within the bank and may have a value between 0 and 63.
Is there any edge/level high/low configuration on these interrupt
lines? If so, then you'll want a third cell for flags. (I may have
already asked you this question)
+
+Example:
+ interrupt-controller@1070000000000 {
+ compatible = "cavium,octeon-3860-ciu";
+ interrupt-controller;
+ /* Interrupts are specified by two parts:
+ * 1) Controller register (0 or 1)
+ * 2) Bit within the register (0..63)
+ */
+ #interrupt-cells =<2>;
+ reg =<0x10700 0x00000000 0x0 0x7000>;
+ };
diff --git a/Documentation/devicetree/bindings/mips/cavium/compact-flash.txt b/Documentation/devicetree/bindings/mips/cavium/compact-flash.txt
new file mode 100644
index 0000000..84972a3
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/compact-flash.txt
@@ -0,0 +1,31 @@
+* Compact Flash
+
+The Cavium Compact Flash device is connected to the Octeon Boot Bus,
+and is thus a child of the Boot Bus device. It can read and write
+industry standard compact flash devices.
+
+Properties:
+- compatible: "cavium,ebt3000-compact-flash";
+
+ Compatibility with many Cavium evaluation boards.
+
+- reg: The base address of the the CF chip select banks. Depending on
+ the device configuration, there may be one or two banks.
+
+- bus-width: The width of the connection to the CF devices. Valid
+ values are 8 and 16.
+
+- true-ide: Mode of the CF connection. Valid values are 1 - True IDE,
+ 0 - not True IDE.
Often, booleans like this are encoded based on whether or not the
property is present. ie. "cavium,true-ide;" turns on true-ide mode.
+
+- dma-engine-handle: Optional, a phandle for the DMA Engine connected
+ to this device.
In general, if you're defining new device-specific properties, it is
good practice to prefix them with "cavium,"
diff --git a/Documentation/devicetree/bindings/mips/cavium/gpio.txt b/Documentation/devicetree/bindings/mips/cavium/gpio.txt
new file mode 100644
index 0000000..21b989a
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/gpio.txt
@@ -0,0 +1,48 @@
+* General Purpose Input Output (GPIO) bus.
+
+Properties:
+- compatible: "cavium,octeon-3860-gpio"
+
+ Compatibility with all cn3XXX, cn5XXX and cn6XXX SOCs.
+
+- reg: The base address of the GPIO unit's register bank.
+
+- gpio-controller: This is a GPIO controller.
+
+- #gpio-cells: Must be<2>. The first cell is the GPIO pin.
Should also state what the meaning of the 2nd cell is.
diff --git a/Documentation/devicetree/bindings/mips/cavium/mix.txt b/Documentation/devicetree/bindings/mips/cavium/mix.txt
new file mode 100644
index 0000000..2a91a33
--- /dev/null
+++ b/Documentation/devicetree/bindings/mips/cavium/mix.txt
@@ -0,0 +1,40 @@
+* MIX Ethernet controller.
+
+Properties:
+- compatible: "cavium,octeon-5750-mix"
+
+ Compatibility with all cn5XXX and cn6XXX SOCs populated with MIX
+ devices.
+
+- reg: The base addresses of four seperate register banks. The first
sp. separate.