Re: [PATCH 4/7] perf, x86: Implement IBS interrupt handler

[Peter Zijlstra]

On Mon, 2011-08-01 at 07:32 +0200, Robert Richter wrote:
> > So IBS cannot trigger the whole unknown NMI business? Wouldn't ibs_op
> > triggering while ibs_fetch just started latch the NMI line, the
> > in-progress NMI would handle both, and we then end up with a spare NMI?
> 
> Ok, I will run some excessive testing of this. If this turns out to be
> a problem I will change the code. Could this be on top of this patch
> set then? 

Sure, if you somehow end up duplicating some logic I think you know
about this common.c file you proposed ;-)

I kinda lost the current state of affairs wrt spurious NMIs, I think
there's still a few reports out there. I recently read through some
Intel errata and found the Intel PMU can send double PMIs under some
circumstances (just to keep life interesting).

I also haven't checked up on what the perf_event_nmi_handler() magic
looks today, so I can't say if its a problem or not, but I thought I'd
just mention it.

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