ARMv7 MMU and cache enabling code in boot/compressed/head.S

[Moon Hwa Hong]

Hi!

I started arm linux kernel hacking.
I can't understand 554 line.
I think that 554 line is not necessary.
Because ISB instruction(556 line) makes synchronization between 553 and 557.
Please advice to me.


530 __armv7_mmu_cache_on:
.
.
.
553         mcr p15, 0, r0, c1, c0, 0   @ load control register
554         mrc p15, 0, r0, c1, c0, 0   @ and read it back
555         mov r0, #0
556         mcr p15, 0, r0, c7, c5, 4   @ ISB
557         mov pc, r12

Have a nice day.

MH Hong.
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