Re: TLB flush question (x86_64)

[Borislav Petkov]

On Sat, Sep 17, 2011 at 07:37:59PM -0400, Brian Gerst wrote:
> On Sat, Sep 17, 2011 at 3:12 PM, Andreas Mohr <andi@xxxxxxxx> wrote:
> > Hi,
> >
> > decided to reply since there hasn't been any activity yet.
> >
> >> Is there any particular reason why
> >> the entire address space is flushed from the tlb while only a range of
> >> virtual address space was supposedly required to be flushed?
> >
> > While this particular function has actually changed in less medieval
> > kernel versions, it would be nice if someone knew an answer to that,
> > especially since TLB activity may have grave performance implications.
> >
> 
> x86 hardware can only flush single pages or the whole TLB.  It would
> be possible to loop over a small set of pages and invalidate each one,
> but the threshold for where that becomes more efficient than flushing
> everything is difficult to determine.

... also, TLBs in current CPUs are highly optimized beasts so that the
cost of a full rewalk is paid only very seldomly by caching even partial
translations in lower level TLBs (L2), etc.

And also, flush_tlb_mm ends up modifying CR3 which doesn't flush the
global mappings.

-- 
Regards/Gruss,
    Boris.
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