Re: [PATCH 1/3] ASoC: wm8940: Fix setting PLL Output clock division ratio

[Girdwood, Liam]

On 24 October 2011 04:32, Axel Lin <axel.lin@xxxxxxxxx> wrote:
> According to the datasheet:
> The PLL Output clock division ratio is controlled by BIT[5:4] of
> WM8940_GPIO register(08h).
> Current code read/write the WM8940_ADDCNTRL(07h) register which is wrong.
>
> Signed-off-by: Axel Lin <axel.lin@xxxxxxxxx>
> ---
> Âsound/soc/codecs/wm8940.c | Â Â4 ++--
> Â1 files changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/sound/soc/codecs/wm8940.c b/sound/soc/codecs/wm8940.c
> index a4abfdf..3cc3bce 100644
> --- a/sound/soc/codecs/wm8940.c
> +++ b/sound/soc/codecs/wm8940.c
> @@ -627,8 +627,8 @@ static int wm8940_set_dai_clkdiv(struct snd_soc_dai *codec_dai,
> Â Â Â Â Â Â Â Âret = snd_soc_write(codec, WM8940_CLOCK, reg | (div << 5));
> Â Â Â Â Â Â Â Âbreak;
> Â Â Â Âcase WM8940_OPCLKDIV:
> - Â Â Â Â Â Â Â reg = snd_soc_read(codec, WM8940_ADDCNTRL) & 0xFFCF;
> - Â Â Â Â Â Â Â ret = snd_soc_write(codec, WM8940_ADDCNTRL, reg | (div << 4));
> + Â Â Â Â Â Â Â reg = snd_soc_read(codec, WM8940_GPIO) & 0xFFCF;
> + Â Â Â Â Â Â Â ret = snd_soc_write(codec, WM8940_GPIO, reg | (div << 4));
> Â Â Â Â Â Â Â Âbreak;
> Â Â Â Â}
> Â Â Â Âreturn ret;
> --

Acked-by: Liam Girdwood <lrg@xxxxxx>
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