Re: [PATCH 23/23] x86, PCI: add pcibios_root_rescan

[Yinghai Lu]

On Wed, Mar 7, 2012 at 3:32 PM, Bjorn Helgaas <bhelgaas@xxxxxxxxxx> wrote:
>
> What's the reason we need to discover those CPU devices in the first place?
>
> I don't think the current policy of blindly probing for things should
> be continued forever.

Do you want to revert follow commit?

BTW, edac never work on nehalem-ex and westmere-ex.

commit a3170c1f924ce2565c4e160b9b095e65c03b2dc6
Author: Jan Beulich <JBeulich@xxxxxxxxxx>
Date:   Wed Feb 23 10:08:10 2011 +0000

    x86/PCI: derive pcibios_last_bus from ACPI MCFG

    On various newer Intel systems the PCI bus(ses) the non-core devices
    live on aren't getting announced by ACPI except through the bus range
    covered by mmconfig. At least the i7core-edac driver depends on these
    devices getting detected.

    Mauro, could you check whether with this change the Xeon 55xx hack in
    that driver can go away altogether, and with it the bogus exporting of
    pcibios_scan_specific_bus()?

    Signed-off-by: Jan Beulich <jbeulich@xxxxxxxxxx>
    Cc: Mauro Carvalho Chehab <mchehab@xxxxxxxxxx>
    Cc: Aristeu Sergio <arozansk@xxxxxxxxxx>
    Signed-off-by: Jesse Barnes <jbarnes@xxxxxxxxxxxxxxxx>

diff --git a/arch/x86/pci/mmconfig-shared.c b/arch/x86/pci/mmconfig-shared.c
index e282886..750c346 100644
--- a/arch/x86/pci/mmconfig-shared.c
+++ b/arch/x86/pci/mmconfig-shared.c
@@ -606,6 +606,16 @@ static void __init __pci_mmcfg_init(int early)
        if (list_empty(&pci_mmcfg_list))
                return;

+       if (pcibios_last_bus < 0) {
+               const struct pci_mmcfg_region *cfg;
+
+               list_for_each_entry(cfg, &pci_mmcfg_list, list) {
+                       if (cfg->segment)
+                               break;
+                       pcibios_last_bus = cfg->end_bus;
+               }
+       }
+
        if (pci_mmcfg_arch_init())
                pci_probe = (pci_probe & ~PCI_PROBE_MASK) | PCI_PROBE_MMCONF;
        else {
--
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