Re: [PATCH 0/6] Add a per-dimm structure

[Borislav Petkov]

On Wed, Mar 14, 2012 at 10:44:13PM -0300, Mauro Carvalho Chehab wrote:
> As I said, that is easy to implement. The hard part would be what to do with
> the per-csrow/per-branch error counters that exist currently at EDAC.
> 
> From my side, I'm OK to remove them, but, as I said before, existing user tools
> use them,

What are you talking about? Those per-rank counters should be the same
as the per-csrow ch0 and ch1 counters...

> especially because UE errors aren't per-rank/per-dimm on the
> typical case (128 bits cacheline).

It depends - if the 128 bit word comes from a single DIMM (unganged
mode) then you have a per-rank UE.

> Of course, the EDAC logic could increment multiple UE error counters
> in such case, (meaning that an error happened on either one of the
> affected DIMMs/Ranks) but this is a different behavior than the
> current API.

Well, the API should be changed to accomodate such configurations.

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