Re: radeon + DVI->mDP converter + mDP display blank screen issuesince 3.0
From: Alex Deucher
Date: Fri Mar 23 2012 - 10:59:30 EST
On Thu, Mar 22, 2012 at 8:49 AM, Lennert Buytenhek
<buytenh@xxxxxxxxxxxxxx> wrote:
> Hi!
>
> Since Linux 3.0, a system with a Radeon HD 5450 (1002:68f9) connected
> to a 27" Apple LED cinema display via an Atlona AT-DP400 Dual Link DVI
> to Mini DisplayPort converter has started to stop giving screen
> output on switching from text mode to graphical framebuffer during
> system startup.
>
> I finally had some time to look at this, and it seems to have stopped
> working after this commit:
>
> commit df271bec805b42527d864777ed035fcbb42e76c0
> Author: Alex Deucher <alexdeucher@xxxxxxxxx>
> Date: Fri May 20 04:34:15 2011 -0400
>
> drm/radeon/kms: properly handle bpc >8 in atom command tables
>
> Signed-off-by: Alex Deucher <alexdeucher@xxxxxxxxx>
> Signed-off-by: Dave Airlie <airlied@xxxxxxxxxx>
>
> ...and with the patch below (i.e. reverting part of the commit above)
> applied to 3.3 I get screen output again.
>
> Even though the monitor seems to have an 8 bit panel, it reports 10
> bits per channel in its EDID:
>
> [...]
> Manufacturer: APP Model 9226 Serial Number 41959462
> Made week 38 of 2010
> EDID version: 1.4
> Digital display
> 10 bits per primary color channel
> DisplayPort interface
> Maximum image size: 60 cm x 34 cm
> [...]
>
> The (active, dual link) DVI->mDP converter spec sheet says it supports
> 24 bit color, and I'm guessing that it can't deal with 30. Is the
> converter at fault here for passing through the EDID unchanged?
>
> Also, what would be the right way to handle this, a kernel command
> line or module option to limit color depth or something like that?
> ("Buy a video card with DP output." is a valid answer, I suppose.)
>
> I have no clue at all about graphics, and I have no idea whatsoever
> what I'm doing here, but I just wanted to post this somewhere for
> Google to find in case someone else runs into this!
I've inquired with out display team on how to best handle this. In
the meantime, it's probably best to just default to 8 bpc. Does the
attached patch fix your issue?
Alex
>
>
> thanks,
> Lennert
>
>
>
> diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
> index 742f17f..77a6a04 100644
> --- a/drivers/gpu/drm/radeon/atombios_crtc.c
> +++ b/drivers/gpu/drm/radeon/atombios_crtc.c
> @@ -513,11 +513,9 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
> struct radeon_device *rdev = dev->dev_private;
> struct drm_encoder *encoder = NULL;
> struct radeon_encoder *radeon_encoder = NULL;
> - struct drm_connector *connector = NULL;
> u32 adjusted_clock = mode->clock;
> int encoder_mode = 0;
> u32 dp_clock = mode->clock;
> - int bpc = 8;
> bool is_duallink = false;
>
> /* reset the pll flags */
> @@ -549,13 +547,11 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
> list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
> if (encoder->crtc == crtc) {
> radeon_encoder = to_radeon_encoder(encoder);
> - connector = radeon_get_connector_for_encoder(encoder);
> - if (connector && connector->display_info.bpc)
> - bpc = connector->display_info.bpc;
> encoder_mode = atombios_get_encoder_mode(encoder);
> is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
> if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
> (radeon_encoder_get_dp_bridge_encoder_id(encoder) != ENCODER_OBJECT_ID_NONE)) {
> + struct drm_connector *connector = radeon_get_connector_for_encoder(encoder);
> if (connector) {
> struct radeon_connector *radeon_connector = to_radeon_connector(connector);
> struct radeon_connector_atom_dig *dig_connector =
> @@ -645,7 +641,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
> if (encoder_mode == ATOM_ENCODER_MODE_HDMI)
> /* deep color support */
> args.v3.sInput.usPixelClock =
> - cpu_to_le16((mode->clock * bpc / 8) / 10);
> + cpu_to_le16(mode->clock / 10);
> if (dig->coherent_mode)
> args.v3.sInput.ucDispPllConfig |=
> DISPPLL_CONFIG_COHERENT_MODE;
> @@ -753,7 +749,6 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
> u32 fb_div,
> u32 frac_fb_div,
> u32 post_div,
> - int bpc,
> bool ss_enabled,
> struct radeon_atom_ss *ss)
> {
> @@ -817,15 +812,6 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
> args.v5.ucMiscInfo = 0; /* HDMI depth, etc. */
> if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
> args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_REF_DIV_SRC;
> - switch (bpc) {
> - case 8:
> - default:
> - args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_24BPP;
> - break;
> - case 10:
> - args.v5.ucMiscInfo |= PIXEL_CLOCK_V5_MISC_HDMI_30BPP;
> - break;
> - }
> args.v5.ucTransmitterID = encoder_id;
> args.v5.ucEncoderMode = encoder_mode;
> args.v5.ucPpll = pll_id;
> @@ -839,21 +825,6 @@ static void atombios_crtc_program_pll(struct drm_crtc *crtc,
> args.v6.ucMiscInfo = 0; /* HDMI depth, etc. */
> if (ss_enabled && (ss->type & ATOM_EXTERNAL_SS_MASK))
> args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_REF_DIV_SRC;
> - switch (bpc) {
> - case 8:
> - default:
> - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_24BPP;
> - break;
> - case 10:
> - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_30BPP;
> - break;
> - case 12:
> - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_36BPP;
> - break;
> - case 16:
> - args.v6.ucMiscInfo |= PIXEL_CLOCK_V6_MISC_HDMI_48BPP;
> - break;
> - }
> args.v6.ucTransmitterID = encoder_id;
> args.v6.ucEncoderMode = encoder_mode;
> args.v6.ucPpll = pll_id;
> @@ -885,7 +856,6 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
> int encoder_mode = 0;
> struct radeon_atom_ss ss;
> bool ss_enabled = false;
> - int bpc = 8;
>
> list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
> if (encoder->crtc == crtc) {
> @@ -922,7 +892,6 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
> struct radeon_connector_atom_dig *dig_connector =
> radeon_connector->con_priv;
> int dp_clock;
> - bpc = connector->display_info.bpc;
>
> switch (encoder_mode) {
> case ATOM_ENCODER_MODE_DP_MST:
> @@ -995,7 +964,7 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
>
> atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
> encoder_mode, radeon_encoder->encoder_id, mode->clock,
> - ref_div, fb_div, frac_fb_div, post_div, bpc, ss_enabled, &ss);
> + ref_div, fb_div, frac_fb_div, post_div, ss_enabled, &ss);
>
> if (ss_enabled) {
> /* calculate ss amount and step size */
> @@ -1587,7 +1556,7 @@ static void atombios_crtc_disable(struct drm_crtc *crtc)
> case ATOM_PPLL2:
> /* disable the ppll */
> atombios_crtc_program_pll(crtc, radeon_crtc->crtc_id, radeon_crtc->pll_id,
> - 0, 0, ATOM_DISABLE, 0, 0, 0, 0, 0, false, &ss);
> + 0, 0, ATOM_DISABLE, 0, 0, 0, 0, false, &ss);
> break;
> default:
> break;
> _______________________________________________
> dri-devel mailing list
> dri-devel@xxxxxxxxxxxxxxxxxxxxx
> http://lists.freedesktop.org/mailman/listinfo/dri-devel
From 22ca454eb749968f266d6788a5f4778acc08cc66 Mon Sep 17 00:00:00 2001
From: Alex Deucher <alexander.deucher@xxxxxxx>
Date: Fri, 23 Mar 2012 10:54:45 -0400
Subject: [PATCH] drm/radeon/kms/atom: force bpc to 8 for now
Using the bpc (bits per color) specified by the monitor
can cause problems in some cases. Until we get a better
handle on how to deal with those cases, just use a bpc of 8.
Reported-by: Lennert Buytenhek <buytenh@xxxxxxxxxxxxxx>
Signed-off-by: Alex Deucher <alexander.deucher@xxxxxxx>
Cc: stable@xxxxxxxxxx
---
drivers/gpu/drm/radeon/atombios_crtc.c | 8 +++++---
drivers/gpu/drm/radeon/atombios_dp.c | 3 +++
drivers/gpu/drm/radeon/atombios_encoders.c | 4 ++--
3 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 083b3ea..b5ff1f7 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -588,8 +588,8 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
if (encoder->crtc == crtc) {
radeon_encoder = to_radeon_encoder(encoder);
connector = radeon_get_connector_for_encoder(encoder);
- if (connector && connector->display_info.bpc)
- bpc = connector->display_info.bpc;
+ /* if (connector && connector->display_info.bpc)
+ bpc = connector->display_info.bpc; */
encoder_mode = atombios_get_encoder_mode(encoder);
is_duallink = radeon_dig_monitor_is_duallink(encoder, mode->clock);
if ((radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT | ATOM_DEVICE_DFP_SUPPORT)) ||
@@ -965,7 +965,9 @@ static void atombios_crtc_set_pll(struct drm_crtc *crtc, struct drm_display_mode
struct radeon_connector_atom_dig *dig_connector =
radeon_connector->con_priv;
int dp_clock;
- bpc = connector->display_info.bpc;
+
+ /* if (connector->display_info.bpc)
+ bpc = connector->display_info.bpc; */
switch (encoder_mode) {
case ATOM_ENCODER_MODE_DP_MST:
diff --git a/drivers/gpu/drm/radeon/atombios_dp.c b/drivers/gpu/drm/radeon/atombios_dp.c
index 6c62be2..c57d856 100644
--- a/drivers/gpu/drm/radeon/atombios_dp.c
+++ b/drivers/gpu/drm/radeon/atombios_dp.c
@@ -405,10 +405,13 @@ static void dp_get_adjust_train(u8 link_status[DP_LINK_STATUS_SIZE],
/* get bpc from the EDID */
static int convert_bpc_to_bpp(int bpc)
{
+#if 0
if (bpc == 0)
return 24;
else
return bpc * 3;
+#endif
+ return 24;
}
/* get the max pix clock supported by the link rate and lane num */
diff --git a/drivers/gpu/drm/radeon/atombios_encoders.c b/drivers/gpu/drm/radeon/atombios_encoders.c
index 468b874..e607c4d 100644
--- a/drivers/gpu/drm/radeon/atombios_encoders.c
+++ b/drivers/gpu/drm/radeon/atombios_encoders.c
@@ -541,7 +541,7 @@ atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mo
dp_clock = dig_connector->dp_clock;
dp_lane_count = dig_connector->dp_lane_count;
hpd_id = radeon_connector->hpd.hpd;
- bpc = connector->display_info.bpc;
+ /* bpc = connector->display_info.bpc; */
}
/* no dig encoder assigned */
@@ -1159,7 +1159,7 @@ atombios_external_encoder_setup(struct drm_encoder *encoder,
dp_lane_count = dig_connector->dp_lane_count;
connector_object_id =
(radeon_connector->connector_object_id & OBJECT_ID_MASK) >> OBJECT_ID_SHIFT;
- bpc = connector->display_info.bpc;
+ /* bpc = connector->display_info.bpc; */
}
memset(&args, 0, sizeof(args));
--
1.7.7.5