Re: [PATCH v7 2/4] MIPS: Octeon: Setup irq_domains for interrupts.

[David Daney]

On 03/28/2012 03:31 PM, Grant Likely wrote:
> On Mon, 26 Mar 2012 12:31:19 -0700, David Daney<ddaney.cavm@xxxxxxxxx>  wrote:
> > From: David Daney<david.daney@xxxxxxxxxx>
> >
> > Create two domains.  One for the GPIO lines, and the other for on-chip
> > sources.
> >
> > Signed-off-by: David Daney<david.daney@xxxxxxxxxx>
> > ---
> [...]
> > +struct octeon_irq_gpio_domain_data {
> > +	unsigned int base_hwirq;
> > +};
>
> Hmmm...
>
> > +static int octeon_irq_gpio_xlat(struct irq_domain *d,
> > +				struct device_node *node,
> > +				const u32 *intspec,
> > +				unsigned int intsize,
> > +				unsigned long *out_hwirq,
> > +				unsigned int *out_type)
> > +{
> [...]
> > +	*out_hwirq = gpiod->base_hwirq + pin;
>
> ...base_hwirq is only used here...
>
> [...]
> > +		gpiod = kzalloc(sizeof (*gpiod), GFP_KERNEL);
> > +		if (gpiod) {
> > +			/* gpio domain host_data is the base hwirq number. */
> > +			gpiod->base_hwirq = 16;
> > +			irq_domain_add_linear(gpio_node, 16,&octeon_irq_domain_gpio_ops, gpiod);
>
> ... and it is unconditionally set to 16.  It looks to me like
> base_hwirq and the associated kzalloc() is unnecessary.

There is a little information asymmetry here.  You don't know that I 
have a patch queued up to add another user of the GPIO irq_domain that 
has a different base_hwirq.

I could re-do this to hard code it, and then add it back.  But it would 
really just be busy work.

David Daney
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