Re: [PATCH RESEND] x86: cache_info: Fix setup of l2/l3 ids

[Ido Yariv]

On Fri, Apr 20, 2012 at 1:09 AM, Ido Yariv <ido@xxxxxxxxxx> wrote:
> From: Shai Fultheim <shai@xxxxxxxxxxx>
>
> On some architectures (such as vSMP), it is possible to have CPUs with a
> different number of cores sharing the same cache.
>
> The current implementation implicitly assumes that all CPUs will have
> the same number of cores sharing caches, and as a result, different CPUs
> can end up with the same l2/l3 ids.
>
> Fix this by masking out the shared cache bits, instead of shifting the
> APICID. By doing so, it is guaranteed that the generated cache ids are
> always unique.
>
> Signed-off-by: Shai Fultheim <shai@xxxxxxxxxxx>
> [ido@xxxxxxxxxx: rebased, simplified, and reworded the commit message]
> Signed-off-by: Ido Yariv <ido@xxxxxxxxxx>

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