Re: [PATCH 4/7] perf/x86-ibs: Add support for IBS pseudo events

[Stephane Eranian]

Robert,

There is something I don't quite understand with those pseudo-events.
Is it the case that by construction, it means you can only measure
on pseudo-event at a time? Supposed I want to look at cache-misses.
For each miss, I'd like to know where it missed, any TLB impacts. All
of that in one run with no multiplexing. Can I do this with your pseudo-events?



On Wed, May 2, 2012 at 8:26 PM, Robert Richter <robert.richter@xxxxxxx> wrote:
> This patch implements support for IBS pseudo events. Pseudo events are
> derived from an IBS sample and determined through a combination of one
> or more IBS event flags or values. See here for a full description:
>
> ÂSoftware Optimization Guide for AMD Family 15h Processors
> ÂAppendix F Guide to Instruction-Based Sampling on AMD Family 15h Processors
> ÂAdvanced Micro Devices, Inc.
> ÂPublication No. 47414, Revision 3.06
> ÂJanuary 2012
> Âhttp://support.amd.com/us/Processor_TechDocs/47414_15h_sw_opt_guide.pdf
>
> The list of supported events is provided by perf-list. A pseudo event
> can be set up like this:
>
> Â# perf record -a -e ibs_op:MISPREDICTED_BRANCH ...
>
> The filter rules for IBS samples depending on a pseudo event are also
> described in the document above. The filter is setup in the perf tool
> pmu handler and passed to the kernel via config1/config2 attr values.
> The interface is extendable to pass the pseudo events directly to the
> kernel.
>
> There are some pseudo events capable to count latencies or other
> values. Counting values of such events is not yet supported.
>
> This patch includes kernel and userland changes.
>
> Signed-off-by: Robert Richter <robert.richter@xxxxxxx>
> ---
> Âarch/x86/kernel/cpu/perf_event_amd_ibs.c | Â 83 ++++++-
> Âtools/perf/util/pmu-ibs.c        Â| Â433 +++++++++++++++++++++++++-----
> Â2 files changed, 445 insertions(+), 71 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/perf_event_amd_ibs.c b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
> index 03743ad..1675479 100644
> --- a/arch/x86/kernel/cpu/perf_event_amd_ibs.c
> +++ b/arch/x86/kernel/cpu/perf_event_amd_ibs.c
> @@ -478,6 +478,81 @@ static struct perf_ibs perf_ibs_op = {
>    Â.get_count       Â= get_ibs_op_count,
> Â};
>
> +enum ibs_filter_type {
> + Â Â Â IBS_NO_FILTER Â Â Â Â Â = 0,
> + Â Â Â IBS_MATCH_FILTER Â Â Â Â= 1,
> + Â Â Â IBS_ANY_SET_FILTER Â Â Â= 2,
> + Â Â Â IBS_PSEUDO_EVENT Â Â Â Â= 0x0F,
> +};
> +
> +struct ibs_filter {
> + Â Â Â struct {
> +        u16       idx       : 8;
> +        u16       reserved    Â: 4;
> +        u16       type      Â: 4;
> + Â Â Â };
> + Â Â Â union {
> + Â Â Â Â Â Â Â struct {
> + Â Â Â Â Â Â Â Â Â Â Â u8 Â Â Âmask;
> + Â Â Â Â Â Â Â Â Â Â Â u8 Â Â Âmatch;
> + Â Â Â Â Â Â Â };
> + Â Â Â Â Â Â Â u16 Â Â Â Â Â Â any;
> + Â Â Â };
> +};
> +
> +static bool
> +__perf_ibs_sample_matches(struct ibs_filter *filter, void *data, int size)
> +{
> + Â Â Â int left = size;
> +
> + Â Â Â switch (filter->type) {
> + Â Â Â case IBS_MATCH_FILTER:
> + Â Â Â Â Â Â Â left -= sizeof(u8);
> + Â Â Â Â Â Â Â break;
> + Â Â Â case IBS_ANY_SET_FILTER:
> + Â Â Â Â Â Â Â left -= sizeof(u16);
> + Â Â Â Â Â Â Â break;
> + Â Â Â default:
> + Â Â Â Â Â Â Â return false;
> + Â Â Â }
> +
> + Â Â Â left -= filter->idx;
> + Â Â Â if (left < 0)
> + Â Â Â Â Â Â Â return false;
> +
> + Â Â Â switch (filter->type) {
> + Â Â Â case IBS_MATCH_FILTER:
> + Â Â Â Â Â Â Â return ((*(u8*)(data + filter->idx)) & filter->mask) == filter->match;
> + Â Â Â case IBS_ANY_SET_FILTER:
> + Â Â Â Â Â Â Â return (*(u16*)(data + filter->idx)) & filter->any;
> + Â Â Â };
> +
> + Â Â Â return false;
> +}
> +
> +static bool perf_ibs_sample_matches(struct perf_event *event,
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct perf_ibs_data *data)
> +{
> + Â Â Â int i;
> + Â Â Â union {
> + Â Â Â Â Â Â Â struct ibs_filter filter[4];
> + Â Â Â Â Â Â Â u64 Â Â config[2];
> + Â Â Â } f;
> + Â Â Â struct ibs_filter *filter = f.filter;
> +
> + Â Â Â f.config[0] = event->attr.config1;
> + Â Â Â f.config[1] = event->attr.config2;
> +
> + Â Â Â for (i = 0; i < 4; i++, filter++) {
> + Â Â Â Â Â Â Â if (filter->type == IBS_NO_FILTER)
> + Â Â Â Â Â Â Â Â Â Â Â break;
> + Â Â Â Â Â Â Â if (!__perf_ibs_sample_matches(filter, data->regs, data->size))
> + Â Â Â Â Â Â Â Â Â Â Â return false;
> + Â Â Â }
> +
> + Â Â Â return true;
> +}
> +
> Âstatic int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> Â{
> Â Â Â Âstruct cpu_perf_ibs *pcpu = this_cpu_ptr(perf_ibs->pcpu);
> @@ -487,7 +562,7 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> Â Â Â Âstruct perf_raw_record raw;
> Â Â Â Âstruct pt_regs regs;
> Â Â Â Âstruct perf_ibs_data ibs_data;
> - Â Â Â int offset, size, check_rip, offset_max, throttle = 0;
> + Â Â Â int offset, size, check_rip, filter, offset_max, throttle = 0;
> Â Â Â Âunsigned int msr;
> Â Â Â Âu64 *buf, *config, period;
>
> @@ -517,7 +592,8 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> Â Â Â Âsize = 1;
> Â Â Â Âoffset = 1;
> Â Â Â Âcheck_rip = (perf_ibs == &perf_ibs_op && (ibs_caps & IBS_CAPS_RIPINVALIDCHK));
> - Â Â Â if (event->attr.sample_type & PERF_SAMPLE_RAW)
> + Â Â Â filter = (event->attr.config1 != 0);
> + Â Â Â if (filter || (event->attr.sample_type & PERF_SAMPLE_RAW))
> Â Â Â Â Â Â Â Âoffset_max = perf_ibs->offset_max;
> Â Â Â Âelse if (check_rip)
> Â Â Â Â Â Â Â Âoffset_max = 2;
> @@ -532,6 +608,9 @@ static int perf_ibs_handle_irq(struct perf_ibs *perf_ibs, struct pt_regs *iregs)
> Â Â Â Â} while (offset < offset_max);
> Â Â Â Âibs_data.size = sizeof(u64) * size;
>
> + Â Â Â if (filter && !perf_ibs_sample_matches(event, &ibs_data))
> + Â Â Â Â Â Â Â goto out;
> +
> Â Â Â Âregs = *iregs;
> Â Â Â Âif (check_rip && (ibs_data.regs[2] & IBS_RIP_INVALID)) {
> Â Â Â Â Â Â Â Âregs.flags &= ~PERF_EFLAGS_EXACT;
> diff --git a/tools/perf/util/pmu-ibs.c b/tools/perf/util/pmu-ibs.c
> index 07acb82..604cb8c 100644
> --- a/tools/perf/util/pmu-ibs.c
> +++ b/tools/perf/util/pmu-ibs.c
> @@ -12,84 +12,378 @@
> Â#include <linux/compiler.h>
> Â#include "pmu.h"
>
> -static const char *events[] = {
> - Â Â Â "ibs_fetch:2M_PAGE",
> - Â Â Â "ibs_fetch:4K_PAGE",
> - Â Â Â "ibs_fetch:ABORTED",
> - Â Â Â "ibs_fetch:ALL",
> - Â Â Â "ibs_fetch:ATTEMPTED",
> - Â Â Â "ibs_fetch:COMPLETED",
> - Â Â Â "ibs_fetch:ICACHE_HITS",
> - Â Â Â "ibs_fetch:ICACHE_MISSES",
> - Â Â Â "ibs_fetch:ITLB_HITS",
> - Â Â Â "ibs_fetch:KILLED",
> - Â Â Â "ibs_fetch:L1_ITLB_MISSES_L2_ITLB_HITS",
> - Â Â Â "ibs_fetch:L1_ITLB_MISSES_L2_ITLB_MISSES",
> - Â Â Â "ibs_fetch:LATENCY",
> - Â Â Â "ibs_op:ALL",
> - Â Â Â "ibs_op:ALL_LOAD_STORE",
> - Â Â Â "ibs_op:BANK_CONF_LOAD",
> - Â Â Â "ibs_op:BANK_CONF_STORE",
> - Â Â Â "ibs_op:BRANCH_RETIRED",
> - Â Â Â "ibs_op:CANCELLED",
> - Â Â Â "ibs_op:COMP_TO_RET",
> - Â Â Â "ibs_op:DATA_CACHE_MISS",
> - Â Â Â "ibs_op:DATA_HITS",
> - Â Â Â "ibs_op:DC_LOAD_LAT",
> - Â Â Â "ibs_op:DCUC_MEM_ACC",
> - Â Â Â "ibs_op:DCWC_MEM_ACC",
> - Â Â Â "ibs_op:FORWARD",
> - Â Â Â "ibs_op:L1_DTLB_1G",
> - Â Â Â "ibs_op:L1_DTLB_2M",
> - Â Â Â "ibs_op:L1_DTLB_4K",
> - Â Â Â "ibs_op:L1_DTLB_HITS",
> - Â Â Â "ibs_op:L1_DTLB_MISS_L2_DTLB_HIT",
> - Â Â Â "ibs_op:L1_L2_DTLB_MISS",
> - Â Â Â "ibs_op:L2_DTLB_1G",
> - Â Â Â "ibs_op:L2_DTLB_2M",
> - Â Â Â "ibs_op:L2_DTLB_4K",
> - Â Â Â "ibs_op:LOAD",
> - Â Â Â "ibs_op:LOCKED",
> - Â Â Â "ibs_op:MAB_HIT",
> - Â Â Â "ibs_op:MISALIGNED_DATA_ACC",
> - Â Â Â "ibs_op:MISPREDICTED_BRANCH",
> - Â Â Â "ibs_op:MISPREDICTED_BRANCH_TAKEN",
> - Â Â Â "ibs_op:MISPREDICTED_RETURNS",
> - Â Â Â "ibs_op:NB_CACHE_MODIFIED",
> - Â Â Â "ibs_op:NB_CACHE_OWNED",
> - Â Â Â "ibs_op:NB_LOCAL_CACHE",
> - Â Â Â "ibs_op:NB_LOCAL_CACHE_LAT",
> - Â Â Â "ibs_op:NB_LOCAL_DRAM",
> - Â Â Â "ibs_op:NB_LOCAL_L3",
> - Â Â Â "ibs_op:NB_LOCAL_ONLY",
> - Â Â Â "ibs_op:NB_LOCAL_OTHER",
> - Â Â Â "ibs_op:NB_REMOTE_CACHE",
> - Â Â Â "ibs_op:NB_REMOTE_CACHE_LAT",
> - Â Â Â "ibs_op:NB_REMOTE_DRAM",
> - Â Â Â "ibs_op:NB_REMOTE_ONLY",
> - Â Â Â "ibs_op:NB_REMOTE_OTHER",
> - Â Â Â "ibs_op:RESYNC",
> - Â Â Â "ibs_op:RETURNS",
> - Â Â Â "ibs_op:STORE",
> - Â Â Â "ibs_op:TAG_TO_RETIRE",
> - Â Â Â "ibs_op:TAKEN_BRANCH",
> - Â Â Â NULL
> +enum ibs_filter_type {
> + Â Â Â IBS_NO_FILTER Â Â Â Â Â = 0,
> + Â Â Â IBS_MATCH_FILTER Â Â Â Â= 1,
> + Â Â Â IBS_ANY_SET_FILTER Â Â Â= 2,
> + Â Â Â IBS_PSEUDO_EVENT Â Â Â Â= 0x0F,
> +};
> +
> +struct ibs_filter {
> + Â Â Â struct {
> +        __u16      idx       : 8;
> +        __u16      reserved    Â: 4;
> +        __u16      type      Â: 4;
> + Â Â Â };
> + Â Â Â union {
> + Â Â Â Â Â Â Â struct {
> + Â Â Â Â Â Â Â Â Â Â Â __u8 Â Âmask;
> + Â Â Â Â Â Â Â Â Â Â Â __u8 Â Âmatch;
> + Â Â Â Â Â Â Â };
> + Â Â Â Â Â Â Â __u16 Â Â Â Â Â any;
> + Â Â Â };
> +};
> +
> +struct ibs_event {
> + Â Â Â __u16 Â Â Â Â Â Â Â Â Â id;
> +    const char       Â*name;
> +    const char       Â*desc;
> + Â Â Â union {
> + Â Â Â Â Â Â Â __u16 Â Â Â Â Â pseudo_event;
> + Â Â Â Â Â Â Â __u64 Â Â Â Â Â config;
> + Â Â Â Â Â Â Â struct ibs_filter filter[2];
> + Â Â Â };
> +};
> +
> +#define IBS_FETCH_CTL Â Â Â Â Â0
> +#define IBS_OP_DATA Â Â Â Â Â Â2
> +#define IBS_OP_DATA2 Â Â Â Â Â 3
> +#define IBS_OP_DATA3 Â Â Â Â Â 4
> +
> +#define IBS_IDX(reg, bit) Â Â Â((reg)<<3)+((bit)>>3)
> +#define IBS_MASK(bit, m) Â Â Â (0xFF&m)
> +#define IBS_MASK16(bit, m) Â Â (0xFFFF&m)
> +#define IBS_FILTER_MATCH_ANY() { { 0, 0, 0 }, { .any = 0 } }
> +
> +#define IBS_FILTER_ANY_SET(reg, bit, m) Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_ANY_SET_FILTER,          \
> +        .idx  Â= IBS_IDX(reg, bit),          Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .any  Â= IBS_MASK16(bit, m),          \
> + Â Â Â Â Â Â Â } Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â },
> +
> +#define IBS_FILTER_ALL_CLEAR(reg, bit, m) Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg, bit),          Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit, m),           \
> + Â Â Â Â Â Â Â .match = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â }, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg, (bit) + 8),       Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit, (m) >> 8),       Â\
> + Â Â Â Â Â Â Â .match Â= 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â },
> +
> +#define IBS_FILTER_ALL_SET(reg, bit, m) Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg, bit),          Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit, m),           \
> + Â Â Â Â Â Â Â .match Â= IBS_MASK(bit, m), Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â },
> +
> +#define IBS_FILTER_MATCH(reg, bit, m, v) Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg, bit),          Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit, m),           \
> + Â Â Â Â Â Â Â .match Â= IBS_MASK(bit, v), Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â },
> +
> +#define IBS_FILTER_MATCH2(reg, reg2, bit, bit2, m, m2, v, v2) Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg, bit),          Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit, m),           \
> + Â Â Â Â Â Â Â .match Â= IBS_MASK(bit, v), Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â }, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .type  = IBS_MATCH_FILTER,           \
> +        .idx  Â= IBS_IDX(reg2, bit2),         Â\
> + Â Â Â Â Â Â Â .reserved = 0, Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â Â Â Â Â },{{ Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> +        .mask  = IBS_MASK(bit2, m2),          \
> + Â Â Â Â Â Â Â .match Â= IBS_MASK(bit2, v2), Â Â Â Â Â Â Â Â Â \
> + Â Â Â Â Â Â Â }} Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â\
> + Â Â Â }
> +
> +#define IBS_EVENT(i, n, d) Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> + Â Â Â { Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â \
> +        .id   = (i),                 Â\
> +        .name  = (n),                 Â\
> +        .desc  = (d),                 Â\
> + Â Â Â Â Â Â Â { .filter = { IBS_FILTER_##i } }, Â Â Â Â Â Â Â \
> + Â Â Â }
> +#define IBS_FILTER(type, args...) Â Â Â Â Â Â ÂIBS_FILTER_##type(args)
> +
> +/*
> + * ID  Name               Derivation
> + *
> + * F000 IBS fetch samples        ÂNumber of all IBS fetch samples
> + * F001 IBS fetch killed         Number of killed IBS fetch samples
> + * F002 IBS fetch attempted       ÂNumber of non-killed IBS fetch samples
> + * F003 IBS fetch completed       ÂIbsFetchComp
> + * F004 IBS fetch aborted        Â~IbsFetchComp
> + * F005 IBS L1 ITLB hit         Â~IbsL1TlbMiss & IbsPhyAddrValid
> + * F006 IBS L1 ITLB miss, L2 ITLB hit  ÂIbsL1TlbMiss & ~IbsL2TlbMiss
> + * F007 IBS L1 ITLB miss, L2 ITLB miss  IbsL1TlbMiss & IbsL2TlbMiss
> + * F008 IBS instruction cache miss    IbsIcMiss
> + * F009 IBS instruction cache hit    ÂIbsFetchComp & ~IbsIcMiss
> + * F00A IBS 4K page translation     ÂIbsL1TlbPgSz=0 & IbsPhyAddrValid
> + * F00B IBS 2M page translation     ÂIbsL1TlbPgSz=1 & IbsPhyAddrValid
> + * F00C IBS 1G page translation     ÂIbsL1TlbPgSz=2 & IbsPhyAddrValid
> + * F00D Reserved
> + * F00E IBS fetch latency        ÂIbsfetchLat
> + */
> +#define IBS_FILTER_0xf000 IBS_FILTER(MATCH_ANY)
> +#define IBS_FILTER_0xf001 IBS_FILTER(ALL_CLEAR, Â Â Â ÂIBS_FETCH_CTL, Â48, 0x019c)
> +#define IBS_FILTER_0xf002 IBS_FILTER(ANY_SET, ÂIBS_FETCH_CTL, Â48, 0x019c)
> +#define IBS_FILTER_0xf003 IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x04, 0x04)
> +#define IBS_FILTER_0xf004 IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x04, 0x00)
> +#define IBS_FILTER_0xf005 IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x90, 0x10)
> +#define IBS_FILTER_0xf006 IBS_FILTER(MATCH2, Â IBS_FETCH_CTL, IBS_FETCH_CTL, 56, 48, 0x01, 0x80, 0x00, 0x80)
> +#define IBS_FILTER_0xf007 IBS_FILTER(MATCH2, Â IBS_FETCH_CTL, IBS_FETCH_CTL, 56, 48, 0x01, 0x80, 0x01, 0x80)
> +#define IBS_FILTER_0xf008 IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x08, 0x08)
> +#define IBS_FILTER_0xf009 IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x0C, 0x04)
> +#define IBS_FILTER_0xf00a IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x70, 0x10)
> +#define IBS_FILTER_0xf00b IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x70, 0x30)
> +#define IBS_FILTER_0xf00c IBS_FILTER(MATCH, Â ÂIBS_FETCH_CTL, Â48, 0x70, 0x60)
> +#if 0
> +#define IBS_FILTER_0xf00e IBS_FILTER(COUNT, Â ÂIBS_FETCH_CTL, Â32, 0xffff)
> +#endif
> +
> +/*
> + * ID  Name               Derivation
> + *
> + * F100 IBS all op samples        Number of all IBS op samples
> + * F101 IBS tag to retire cycles     Sum of all tag to retire cycles
> + * F102 ibs completion to retire cycles ÂSum of all completion to retire cycles
> + * F103 IBS branch op          ÂIbsOpBrnRet
> + * F104 IBS mispredicted branch op    IbsOpBrnRet & IbsOpBrnMisp
> + * F105 IBS taken branch op       ÂIbsOpBrnRet & IbsOpBrnTaken
> + * F106 IBS mispredicted taken branch op IbsOpBrnRet & IbsOpBrnTaken & IbsOpBrnMisp
> + * F107 IBS return op          ÂIbsOpReturn
> + * F108 IBS mispredicted return op    IbsOpReturn & IbsOpMispReturn
> + * F109 IBS resync op          ÂIbsOpBrnResync
> + */
> +#define IBS_FILTER_0xf100 IBS_FILTER(MATCH_ANY)
> +#if 0
> +#define IBS_FILTER_0xf101 IBS_FILTER(COUNT, Â ÂIBS_OP_DATA, Â Â16, 0xffff)
> +#define IBS_FILTER_0xf102 IBS_FILTER(COUNT, Â ÂIBS_OP_DATA, Â Â 0, 0xffff)
> +#endif
> +#define IBS_FILTER_0xf103 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x20, 0x20)
> +#define IBS_FILTER_0xf104 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x30, 0x30)
> +#define IBS_FILTER_0xf105 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x28, 0x28)
> +#define IBS_FILTER_0xf106 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x38, 0x38)
> +#define IBS_FILTER_0xf107 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x04, 0x04)
> +#define IBS_FILTER_0xf108 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x06, 0x06)
> +#define IBS_FILTER_0xf109 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA, Â Â32, 0x01, 0x01)
> +
> +/*
> + * ID  Name               Derivation
> + *
> + * F200 IBS All Load/Store Ops      IbsLdOp | IbsStOp
> + * F201 IBS Load Ops           IbsLdOp
> + * F202 IBS Store Ops          ÂIbsStOp
> + * F203 IBS L1 DTLB Hit         Â~IbsDcL1tlbMiss & IbsDcLinAddrValid
> + * F204 IBS L1 DTLB Miss L2 DTLB Hit   IbsDcL1tlbMiss & ~IbsDcL2tlbMiss
> + * F205 IBS L1 DTLB Miss L2 DTLB Miss  ÂIbsDcL1tlbMiss & IbsDcL2tlbMiss
> + * F206 IBS DC Miss           ÂIbsDcMiss
> + * F207 IBS DC Hit            ~IbsDcMiss
> + * F208 IBS Misaligned Access      ÂIbsDcMisAcc
> + * F209 IBS Bank Conflict On Load Op   IbsDcLdBnkCon
> + * F20A Reserved
> + * F20B IBS Store to Load Forwarded   ÂIbsDcStToLdFwd
> + * F20C IBSStore to Load Forwarding Cancelled IbsDcStToLdCan
> + * F20D IBS UC memory access       IbsDcUcMemAcc
> + * F20E IBS WC memory access       IbsDcWcMemAcc
> + * F20F IBS locked operation       IbsDcLockedOp
> + * F210 IBS MAB hit           ÂIbsDcMabHit
> + * F211 IBS L1 DTLB 4K page       Â~IbsDcL1tlbHit2M & ~IbsDcL1tlbHit1G &
> + * Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â IbsDcLinAddrValid
> + * F212 IBS L1 DTLB 2M page       ÂIbsDcL1tlbHit2M & IbsDcLinAddrValid
> + * F213 IBS L1 DTLB 1G page       ÂIbsDcL1tlbHit1G & IbsDcLinAddrValid
> + * F214 Reserved
> + * F215 IBS L2 DTLB 4K page       Â~IbsDcL2tlbMiss & IbsDcL1tlbMiss &
> + * Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â ~IbsDcL1tlbHit2M & lbsDcLinAddrValid
> + * F216 IBS L2 DTLB 2M page       Â~IbsDcL2tlbMiss & IbsDcL1tlbMiss &
> + * Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â IbsDcL1tlbHit2M & lbsDcLinAddrValid
> + * F217 Reserved
> + * F218 Reserved
> + * F219 IBS DC miss load latency     IbsDcMissLat when IbsLdOp & IbsDcMiss
> + */
> +#define IBS_FILTER_0xf200 IBS_FILTER(ANY_SET, ÂIBS_OP_DATA3, Â Â0, 0x0003)
> +#define IBS_FILTER_0xf201 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x01, 0x01)
> +#define IBS_FILTER_0xf202 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x02, 0x02)
> +#define IBS_FILTER_0xf203 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x04, 0x02, 0x00)
> +#define IBS_FILTER_0xf204 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x0C, 0x08)
> +#define IBS_FILTER_0xf205 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x0C, 0x0C)
> +#define IBS_FILTER_0xf206 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x80, 0x80)
> +#define IBS_FILTER_0xf207 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â0, 0x80, 0x00) IBS_FILTER(ANY_SET, Â IBS_OP_DATA3, Â Â0, 0x0003)
> +#define IBS_FILTER_0xf208 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x01, 0x01)
> +#define IBS_FILTER_0xf209 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x02, 0x02)
> +#define IBS_FILTER_0xf20b IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x08, 0x08)
> +#define IBS_FILTER_0xf20c IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x10, 0x10)
> +#define IBS_FILTER_0xf20d IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x40, 0x40)
> +#define IBS_FILTER_0xf20e IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x20, 0x20)
> +#define IBS_FILTER_0xf20f IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â Â8, 0x80, 0x80)
> +#define IBS_FILTER_0xf210 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA3, Â 16, 0x01, 0x01)
> +#define IBS_FILTER_0xf211 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x30, 0x02, 0x00)
> +#define IBS_FILTER_0xf212 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x10, 0x02, 0x10)
> +#define IBS_FILTER_0xf213 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x20, 0x02, 0x20)
> +#define IBS_FILTER_0xf215 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x1C, 0x02, 0x04)
> +#define IBS_FILTER_0xf216 IBS_FILTER(MATCH2, Â IBS_OP_DATA3, IBS_OP_DATA3, 16, 0, 0x02, 0x1C, 0x02, 0x14)
> +#if 0
> +#define IBS_FILTER_0xf219 IBS_FILTER(COUNT, Â ÂIBS_OP_DATA3, Â 32, 0x00FFFF, 0x00FFFF)
> +#endif
> +
> +/*
> + * ID  Name               Derivation
> + *
> + * F240 IBS NB local           ~NbIbsReqDstProc
> + * F241 IBS NB remote          ÂNbIbsReqDstProc
> + * F242 IBS NB local L3 Â Â Â Â Â Â Â Â ÂNbIbsReqSrc=0x1 & ~NbIbsReqDstProc
> + * F243 IBS NB local L1/L2 (intercore) Â NbIbsReqSrc=0x2 & ~NbIbsReqDstProc
> + * F244 IBS NB remote L1/L2/L3 cache   NbIbsReqSrc=0x2 & NbIbsReqDstProc
> + * F245 IBS NB local DRAM Â Â Â Â Â Â Â ÂNbIbsReqSrc=0x3 & ~NbIbsReqDstProc
> + * F246 IBS NB remote DRAM Â Â Â Â Â Â Â NbIbsReqSrc=0x3 & NbIbsReqDstProc
> + * F247 IBS NB local other        NbIbsReqSrc=0x7 & ~NbIbsReqDstProc
> + * F248 IBS NB remote other       ÂNbIbsReqSrc=0x7 & NbIbsReqDstProc
> + * F249 IBS NB cache M state       NbIbsReqSrc=0x2 & ~NbIbsReqCacheHitSt
> + * F24A IBS NB cache O state       NbIbsReqSrc=0x2 & NbIbsReqCacheHitSt
> + * F24B IBS NB local latency       IbsDcMissLat when ~NbIbsReqDstProc
> + * F24C IBS NB remote latency      ÂIbsDcMissLat when NbIbsReqDstProc
> + */
> +#define IBS_FILTER_0xf240 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x10, 0x00) IBS_FILTER(ANY_SET, Â Â IBS_OP_DATA2, Â 0, 0x0007)
> +#define IBS_FILTER_0xf241 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x10, 0x10) IBS_FILTER(ANY_SET, Â Â IBS_OP_DATA2, Â 0, 0x0007)
> +#define IBS_FILTER_0xf242 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x01) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf243 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x02) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf244 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x12) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf245 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x03) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf246 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x13) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf247 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x07) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf248 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x17, 0x17) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf249 IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x27, 0x02) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +#define IBS_FILTER_0xf24a IBS_FILTER(MATCH, Â ÂIBS_OP_DATA2, Â Â0, 0x27, 0x22) IBS_FILTER(MATCH, Â Â Â IBS_OP_DATA3, Â 0, 0x81, 0x81)
> +
> +static struct ibs_event events[] = {
> + Â Â Â IBS_EVENT(0xf000, "ibs_fetch:ALL", "All IBS fetch samples"),
> + Â Â Â IBS_EVENT(0xf001, "ibs_fetch:KILLED", "IBS fetch killed"),
> + Â Â Â IBS_EVENT(0xf002, "ibs_fetch:ATTEMPTED", "IBS fetch attempted"),
> + Â Â Â IBS_EVENT(0xf003, "ibs_fetch:COMPLETED", "IBS fetch completed"),
> + Â Â Â IBS_EVENT(0xf004, "ibs_fetch:ABORTED", "IBS fetch aborted"),
> + Â Â Â IBS_EVENT(0xf005, "ibs_fetch:ITLB_HITS", "IBS ITLB hit"),
> + Â Â Â IBS_EVENT(0xf006, "ibs_fetch:L1_ITLB_MISSES_L2_ITLB_HITS", "IBS L1 ITLB misses (and L2 ITLB hits)"),
> + Â Â Â IBS_EVENT(0xf007, "ibs_fetch:L1_ITLB_MISSES_L2_ITLB_MISSES", "IBS L1 L2 ITLB miss"),
> + Â Â Â IBS_EVENT(0xf008, "ibs_fetch:ICACHE_MISSES", "IBS instruction cache misses"),
> + Â Â Â IBS_EVENT(0xf009, "ibs_fetch:ICACHE_HITS", "IBS instruction cache hit"),
> + Â Â Â IBS_EVENT(0xf00a, "ibs_fetch:4K_PAGE", "IBS 4K page translation"),
> + Â Â Â IBS_EVENT(0xf00b, "ibs_fetch:2M_PAGE", "IBS 2M page translation"),
> + Â Â Â IBS_EVENT(0xf00c, "ibs_fetch:1G_PAGE", "IBS 1G page translation"),
> +#if 0
> + Â Â Â IBS_EVENT(0xf00e, "ibs_fetch:LATENCY", "IBS fetch latency"),
> +#endif
> + Â Â Â IBS_EVENT(0xf100, "ibs_op:ALL", "All IBS op samples"),
> +#if 0
> + Â Â Â IBS_EVENT(0xf101, "ibs_op:TAG_TO_RETIRE", "IBS tag-to-retire cycles"),
> + Â Â Â IBS_EVENT(0xf102, "ibs_op:COMP_TO_RET", "IBS completion-to-retire cycles"),
> +#endif
> + Â Â Â IBS_EVENT(0xf103, "ibs_op:BRANCH_RETIRED", "IBS branch op"),
> + Â Â Â IBS_EVENT(0xf104, "ibs_op:MISPREDICTED_BRANCH", "IBS mispredicted branch op"),
> + Â Â Â IBS_EVENT(0xf105, "ibs_op:TAKEN_BRANCH", "IBS taken branch op"),
> + Â Â Â IBS_EVENT(0xf106, "ibs_op:MISPREDICTED_BRANCH_TAKEN", "IBS mispredicted taken branch op"),
> + Â Â Â IBS_EVENT(0xf107, "ibs_op:RETURNS", "IBS return op"),
> + Â Â Â IBS_EVENT(0xf108, "ibs_op:MISPREDICTED_RETURNS", "IBS mispredicted return op"),
> + Â Â Â IBS_EVENT(0xf109, "ibs_op:RESYNC", "IBS resync op"),
> + Â Â Â IBS_EVENT(0xf200, "ibs_op:ALL_LOAD_STORE", "IBS all load store ops"),
> + Â Â Â IBS_EVENT(0xf201, "ibs_op:LOAD", "IBS load ops"),
> + Â Â Â IBS_EVENT(0xf202, "ibs_op:STORE", "IBS store ops"),
> + Â Â Â IBS_EVENT(0xf203, "ibs_op:L1_DTLB_HITS", "IBS L1 DTLB hit"),
> + Â Â Â IBS_EVENT(0xf204, "ibs_op:L1_DTLB_MISS_L2_DTLB_HIT", "IBS L1 DTLB misses L2 hits"),
> + Â Â Â IBS_EVENT(0xf205, "ibs_op:L1_L2_DTLB_MISS", "IBS L1 and L2 DTLB misses"),
> + Â Â Â IBS_EVENT(0xf206, "ibs_op:DATA_CACHE_MISS", "IBS data cache misses"),
> + Â Â Â IBS_EVENT(0xf207, "ibs_op:DATA_HITS", "IBS data cache hits"),
> + Â Â Â IBS_EVENT(0xf208, "ibs_op:MISALIGNED_DATA_ACC", "IBS misaligned data access"),
> + Â Â Â IBS_EVENT(0xf209, "ibs_op:BANK_CONF_LOAD", "IBS bank conflict on load op"),
> +#if 0
> + Â Â Â IBS_EVENT(0xf20a, "ibs_op:BANK_CONF_STORE", "IBS bank conflict on store op"),
> +#endif
> + Â Â Â IBS_EVENT(0xf20b, "ibs_op:FORWARD", "IBS store-to-load forwarded"),
> + Â Â Â IBS_EVENT(0xf20c, "ibs_op:CANCELLED", "IBS store-to-load cancelled"),
> + Â Â Â IBS_EVENT(0xf20d, "ibs_op:DCUC_MEM_ACC", "IBS UC memory access"),
> + Â Â Â IBS_EVENT(0xf20e, "ibs_op:DCWC_MEM_ACC", "IBS WC memory access"),
> + Â Â Â IBS_EVENT(0xf20f, "ibs_op:LOCKED", "IBS locked operation"),
> + Â Â Â IBS_EVENT(0xf210, "ibs_op:MAB_HIT", "IBS MAB hit"),
> + Â Â Â IBS_EVENT(0xf211, "ibs_op:L1_DTLB_4K", "IBS L1 DTLB 4K page"),
> + Â Â Â IBS_EVENT(0xf212, "ibs_op:L1_DTLB_2M", "IBS L1 DTLB 2M page"),
> + Â Â Â IBS_EVENT(0xf213, "ibs_op:L1_DTLB_1G", "IBS L1 DTLB 1G page"),
> + Â Â Â IBS_EVENT(0xf215, "ibs_op:L2_DTLB_4K", "IBS L2 DTLB 4K page"),
> + Â Â Â IBS_EVENT(0xf216, "ibs_op:L2_DTLB_2M", "IBS L2 DTLB 2M page"),
> +#if 0
> + Â Â Â IBS_EVENT(0xf217, "ibs_op:L2_DTLB_1G", "IBS L2 DTLB 1G page"),
> + Â Â Â IBS_EVENT(0xf219, "ibs_op:DC_LOAD_LAT", "IBS data cache miss load latency"),
> +#endif
> + Â Â Â IBS_EVENT(0xf240, "ibs_op:NB_LOCAL_ONLY", "IBS Northbridge local"),
> + Â Â Â IBS_EVENT(0xf241, "ibs_op:NB_REMOTE_ONLY", "IBS Northbridge remote"),
> + Â Â Â IBS_EVENT(0xf242, "ibs_op:NB_LOCAL_L3", "IBS Northbridge local L3"),
> + Â Â Â IBS_EVENT(0xf243, "ibs_op:NB_LOCAL_CACHE", "IBS Northbridge local core L1 or L2 cache"),
> + Â Â Â IBS_EVENT(0xf244, "ibs_op:NB_REMOTE_CACHE", "IBS Northbridge local core L1, L2, L3 cache"),
> + Â Â Â IBS_EVENT(0xf245, "ibs_op:NB_LOCAL_DRAM", "IBS Northbridge local DRAM"),
> + Â Â Â IBS_EVENT(0xf246, "ibs_op:NB_REMOTE_DRAM", "IBS Northbridge remote DRAM"),
> + Â Â Â IBS_EVENT(0xf247, "ibs_op:NB_LOCAL_OTHER", "IBS Northbridge local APIC MMIO Config PCI"),
> + Â Â Â IBS_EVENT(0xf248, "ibs_op:NB_REMOTE_OTHER", "IBS Northbridge remote APIC MMIO Config PCI"),
> + Â Â Â IBS_EVENT(0xf249, "ibs_op:NB_CACHE_MODIFIED", "IBS Northbridge cache modified state"),
> + Â Â Â IBS_EVENT(0xf24a, "ibs_op:NB_CACHE_OWNED", "IBS Northbridge cache owned state"),
> +#if 0
> + Â Â Â IBS_EVENT(0xf24b, "ibs_op:NB_LOCAL_CACHE_LAT", "IBS Northbridge local cache latency"),
> + Â Â Â IBS_EVENT(0xf24c, "ibs_op:NB_REMOTE_CACHE_LAT", "IBS Northbridge remote cache latency"),
> +#endif
> + Â Â Â { 0, NULL, NULL, { .filter = { IBS_FILTER_MATCH_ANY() } } }
> Â};
>
> Âstatic int ibs_parse_event(struct perf_event_attr *attr, char *sys, char *name)
> Â{
> - Â Â Â const char **event;
> + Â Â Â struct ibs_event *event;
>
> Â Â Â Âif (strcmp("ibs_op", sys) && strcmp("ibs_fetch", sys))
> Â Â Â Â Â Â Â Âreturn -ENOENT;
>
> - Â Â Â for (event = events; *event; event++) {
> - Â Â Â Â Â Â Â if (!strcmp(*event + strlen(sys) + 1, name))
> + Â Â Â for (event = events; event->id; event++) {
> + Â Â Â Â Â Â Â if (!strcmp(event->name + strlen(sys) + 1, name))
> Â Â Â Â Â Â Â Â Â Â Â Âgoto match;
> Â Â Â Â}
>
> Â Â Â Âreturn -EINVAL;
> Âmatch:
> + Â Â Â /* pseudo event found */
> + Â Â Â attr->config1 = event->config;
> Â Â Â Âattr->sample_type = PERF_SAMPLE_CPU;
>
> Â Â Â Âreturn 0;
> @@ -97,13 +391,14 @@ match:
>
> Âstatic void ibs_print_events(const char *sys)
> Â{
> - Â Â Â const char **event;
> + Â Â Â struct ibs_event *event;
>
> Â Â Â Âprintf("\n");
>
> - Â Â Â for (event = events; *event; event++) {
> - Â Â Â Â Â Â Â if (!strncmp(sys, *event, strlen(sys)))
> - Â Â Â Â Â Â Â Â Â Â Â printf(" Â%-50s [PMU event: %s]\n", *event, sys);
> + Â Â Â for (event = events; event->id; event++) {
> + Â Â Â Â Â Â Â if (!strncmp(sys, event->name, strlen(sys)))
> + Â Â Â Â Â Â Â Â Â Â Â printf(" Â%-50s [PMU event: %s, id:0x%x]\n",
> + Â Â Â Â Â Â Â Â Â Â Â Â Â Â Âevent->name, sys, event->id);
> Â Â Â Â}
> Â}
>
> --
> 1.7.8.4
>
>
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