RE: [PATCH 2/2] x86/mce: Add instruction recovery signatures tomce-severity table

[Luck, Tony]

> > I'm trying to figure out a quirk for processors that do generate
> > EIPV=RIPV=0 signature for IFU errors. There are some case where
> > we can work around the lack of EIPV.
>
> __mcheck_cpu_apply_quirks?

The quirk is a bit more extensive than just setting some flag in there
for "if (c->x86 == 6 && c->x86_model == 45)". Sometime EIPV isn't set
because the regs->ip and regs->cs really aren't valid. So  I'll need
to do something like:

	if (we are on Intel family 6 model 45 AND
          this is a UC=1, PCC=0, AR=1, S=1, ADDRV=1, MCACOD=0x150 error AND
	    (virtophys(regs->ip) >> PAGE_SHIFT) == (MC(bank)_ADDR >> PAGE_SHIFT)) {
		/* ok to trust CS & IP */
		m.mcgstatus |= MCG_STATUS_EIPV;
	}
before running through the mce_severity() table lookup.

x86 doesn't seem to have a "virtophys()" that I can find. Closest is lookup_address(vaddr, level)
which gets a pte (which is almost all the work).

Sigh!

-Tony
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