Re: [PATCHv3 0/4] coupled cpuidle state support

[Colin Cross]

On Fri, May 18, 2012 at 12:03 PM, Rafael J. Wysocki <rjw@xxxxxxx> wrote:
> On Friday, May 18, 2012, Santosh Shilimkar wrote:
>> On Tuesday 08 May 2012 06:27 AM, Colin Cross wrote:
>> > On some ARM SMP SoCs (OMAP4460, Tegra 2, and probably more), the
>> > cpus cannot be independently powered down, either due to
>> > sequencing restrictions (on Tegra 2, cpu 0 must be the last to
>> > power down), or due to HW bugs (on OMAP4460, a cpu powering up
>> > will corrupt the gic state unless the other cpu runs a work
>> > around).  Each cpu has a power state that it can enter without
>> > coordinating with the other cpu (usually Wait For Interrupt, or
>> > WFI), and one or more "coupled" power states that affect blocks
>> > shared between the cpus (L2 cache, interrupt controller, and
>> > sometimes the whole SoC).  Entering a coupled power state must
>> > be tightly controlled on both cpus.
>> >
>>
>> [...]
>>
>> > This series has been tested and reviewed by Santosh and Kevin
>> > for OMAP4, which has a cpuidle series ready for 3.5, and Tegra
>> > and Exynos5 patches are in progress.  I think this is ready to
>> > go in.  Lean, are you maintaining a cpuidle tree for linux-next?
>> > If not, I can publish a tree for linux-next, or this could go in
>> > through Arnd's tree.
>>
>> I haven't seen any response so far on who is lining up this
>> series for 3.5 ? Not sure if it made it to linux-next either.
>
> That should be Len, but he's been silent recently.
>
> How urgent is it?

Len silently picked up the last version.  I just posted two fixes to
it, hopefully he'll pick up those too.
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