RE: [PATCH] RAS: Add a tracepoint for reporting memory controllerevents

[Luck, Tony]

> Uuh, that doesn't sound good. Can't you guys make the CMCI run on one
> CPU only? I mean, it is a single CECC, no need to stop all cores on the
> socket for it, right?
>
> Arguably, it'll be best if the core that sees the CECC fires the CMCI
> too and the others continue on their merry way.

That would be best ... but life is more complicated. We can get CMCI for
some processor errors where the error will be logged in a per-core bank,
but for some reason it is hard to have just the threads on that core see
the CMCI. So we just use a shotgun to blast everything standing in the
general direction of the error - so that the one (or two) cpus that can
actually see the error will get the message.  In the normal case when
there is a very low rate of errors, this doesn't do much harm. But it makes
the storm situation when there are many errors a whole lot worse (20x
worse for Westmere with 10 cores * 2 threads).

-Tony 
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