Re: [PATCH] perf: Fix intel shared extra msr allocation

[Stephane Eranian]

On Fri, Jun 1, 2012 at 4:11 PM, Yan, Zheng <zheng.z.yan@xxxxxxxxxxxxxxx> wrote:
> On Fri, Jun 1, 2012 at 5:35 PM, Stephane Eranian <eranian@xxxxxxxxxx> wrote:
>> On Fri, Jun 1, 2012 at 5:20 AM, Yan, Zheng <zheng.z.yan@xxxxxxxxx> wrote:
>>> From: "Yan, Zheng" <zheng.z.yan@xxxxxxxxx>
>>>
>>> intel_shared_reg_get/put_constraints() can be indirectly called
>>> by validate_group(). In that case, they should avoid modifying
>>> the perf_event date structure because the event can be already
>>> in active state. Otherwise the shared extra msr's reference
>>> count will be left in inconsistent state.
>>>
>> I understand the problem but I am wondering if you actually saw
>> it in real life. The reason I am asking is because Âof the way
>> validate_group() collects the events and how they are added
>> to sibling_list. The new event is added at the tail. Thus it will
>> come last, and will get to __intel_shared_reg_get_constraints()
>> last, thus I am wondering if it can really modify the programming
>> on the existing events.
>
> The real problem is from __intel_shared_reg_put_constraints(). it set
> reg->alloc to 0 and decreases fake_cpuc->shared_regs->regs[reg->idx]'s
> reference count. Later when deleting the event, Âput_constraints() will find
> reg->alloc is 0 and it won't decrease the shared msr's reference count.
>
> Run 'perf stat --group -a -C 0 -e LLC-loads -e LLC-stores sleep 1" on
> Nehalem can trigger the bug.
>
And what do you see in this particular example?

I'd like to see the results via libpfm4 and /perf_examples/syst_count:
$ sudo ./syst_count -e offcore_response_0:dmnd_data_rd
-eoffcore_response_0:dmnd_rfo  -p -d 10 -c 0

Should see 50% for each event group.

>>
>> See more comments inline.
>>
>>> Signed-off-by: Zheng Yan <zheng.z.yan@xxxxxxxxx>
>>> ---
>>> Âarch/x86/kernel/cpu/perf_event_intel.c | Â 31 +++++++++++++++++++++++--------
>>> Â1 files changed, 23 insertions(+), 8 deletions(-)
>>>
>>> diff --git a/arch/x86/kernel/cpu/perf_event_intel.c b/arch/x86/kernel/cpu/perf_event_intel.c
>>> index 166546e..10840d0 100644
>>> --- a/arch/x86/kernel/cpu/perf_event_intel.c
>>> +++ b/arch/x86/kernel/cpu/perf_event_intel.c
>>> @@ -1119,11 +1119,21 @@ intel_bts_constraints(struct perf_event *event)
>>> Â Â Â Âreturn NULL;
>>> Â}
>>>
>>> -static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
>>> +static bool intel_try_alt_er(struct perf_event *event, int *idx,
>>> + Â Â Â Â Â Â Â Â Â Â Â Â Â Âint orig_idx, bool fake_cpuc)
>>> Â{
>>> - Â Â Â if (!(x86_pmu.er_flags & ERF_HAS_RSP_1))
>>> + Â Â Â if (!(x86_pmu.er_flags & ERF_HAS_RSP_1) || *idx != orig_idx)
>>> Â Â Â Â Â Â Â Âreturn false;
>>>
>>> + Â Â Â /* don't modify the event structure if the cpuc is faked */
>>> + Â Â Â if (fake_cpuc) {
>>> + Â Â Â Â Â Â Â if (*idx == EXTRA_REG_RSP_0)
>>> + Â Â Â Â Â Â Â Â Â Â Â *idx = EXTRA_REG_RSP_1;
>>> + Â Â Â Â Â Â Â else if (*idx == EXTRA_REG_RSP_1)
>>> + Â Â Â Â Â Â Â Â Â Â Â *idx = EXTRA_REG_RSP_0;
>>> + Â Â Â Â Â Â Â return (*idx != orig_idx);
>>> + Â Â Â }
>>> +
>> I understand that.
>>
>>> Â Â Â Âif (event->hw.extra_reg.idx == EXTRA_REG_RSP_0) {
>>> Â Â Â Â Â Â Â Âevent->hw.config &= ~INTEL_ARCH_EVENT_MASK;
>>> Â Â Â Â Â Â Â Âevent->hw.config |= 0x01bb;
>>> @@ -1139,6 +1149,7 @@ static bool intel_try_alt_er(struct perf_event *event, int orig_idx)
>>> Â Â Â Âif (event->hw.extra_reg.idx == orig_idx)
>>> Â Â Â Â Â Â Â Âreturn false;
>>>
>>> + Â Â Â *idx = event->hw.extra_reg.idx;
>>> Â Â Â Âreturn true;
>>> Â}
>>>
>>> @@ -1155,16 +1166,18 @@ __intel_shared_reg_get_constraints(struct cpu_hw_events *cpuc,
>>> Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â Â struct hw_perf_event_extra *reg)
>>> Â{
>>> Â Â Â Âstruct event_constraint *c = &emptyconstraint;
>>> + Â Â Â struct intel_shared_regs *shared_regs = cpuc->shared_regs;
>>> Â Â Â Âstruct er_account *era;
>>> Â Â Â Âunsigned long flags;
>>> Â Â Â Âint orig_idx = reg->idx;
>>> + Â Â Â int idx = orig_idx;
>>>
>>> - Â Â Â /* already allocated shared msr */
>>> - Â Â Â if (reg->alloc)
>>> + Â Â Â /* shared msr is already allocated and cpuc is not faked */
>>> + Â Â Â if (reg->alloc && shared_regs->core_id != -1)
>>> Â Â Â Â Â Â Â Âreturn NULL; /* call x86_get_event_constraint() */
>>>
>> I don't understand what you need this stuff. Shared_regs is faked as well.
>
> The event can be in active state, we should avoid clearing reg->alloc.
>
> Regards
> Yan, Zheng
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