RE: [Xen-devel] [xen vMCE RFC V0.2] xen vMCE design

[Liu, Jinsong]

Thanks AMD's feedback :)

This vMCE design foils is basically for Intel MCA, involving many details specific to Intel.
I agree that for x86 Intel and AMD can share logic in many fields. However, for MCA logic Intel and AMD are quite different, like
1. MSRs interface, e.g. MCG_CAP, MCi_MICS, MCi_CTL2, etc;
2. error injection, AMD provide NMI/single MCE/broadcast MCE, while in our design only concern broadcast MCE# (and pretend to expose CMCI);
3. MCE handler: currently in xen Intel and AMD mce use different triggle method and mce handler;

Considering the big difference, I suggest we separately provide Intel vMCE and AMD vMCE (i.e. vmce_intel.c and vmce_amd.c).

Thanks,
Jinsong

Christoph Egger wrote:
> Feedback from the AMD side:
> 
> slide 2:
> - PV guests are supposed to install a MCE trap handler
>   which reads the MSR values from struct mcinfo_bank.
>   Hence it is unclear where the #GP should come from.
>   Same for HVM guests which have a PV MCE "driver"
>   (those are very rare in reality).
> 
> slide 3:
> - unclear what "Weird per-domain MSRs" means
> - unclear what "Unnatural MCE injection semantics" means
> 
> slide 4:
> - typo: interace -> interface :-)
> - enable UCR-related capabilities, but only on Intel machines
> - Filter non-SRAO/SRAR banks:
>   Rename it to "Let guest see northbridge bank only to the guest"
> 
> slide 7:
> - ignore/disable CMCI and CTL2 on AMD
> 
> slide 8:
> - Filter non-SRAO/SRAR banks:
>   Rename it to "Let guest see northbridge bank only to the guest"
> - Question: Should we allow the guest to inject errors? Does it make
>   sense?
> - always disable MCi_CTL2 on AMD
> 
> slide 9:
> - Model specific issue: Also affects AMD as some models have
>   l3 cache and some do not.
>   E.g. it does not make sense to report l3 cache errors to guests

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