Re: [PATCH 08/36] AArch64: Kernel booting and initialisation

[Catalin Marinas]

On Thu, Jul 19, 2012 at 06:31:07PM +0100, Christopher Covington wrote:
> On 07/18/2012 02:57 AM, Jon Masters wrote:
> > On 07/06/2012 05:05 PM, Catalin Marinas wrote:
> > 
> >> +- CPU mode
> >> +  All forms of interrupts must be masked in PSTATE.DAIF (Debug, SError,
> >> +  IRQ and FIQ).
> >> +  The CPU must be in either EL2 (RECOMMENDED) or non-secure EL1.
> 
> Why not secure EL1?

Because the secure side does not have virtualisation extensions so you
won't be able to run something like KVM.

> > Even though this stuff is likely to be replaced with the result of some
> > of the other standardization, I'd like it if you'd strongly consider
> > removing the "or non-secure EL1". If you give an inch, someone will take
> > a mile and build a system that enters other than in EL2. Or, something
> > to the effect of "the highest non-secure exception level implemented"
> > would be my preference if you don't want to specify.
> 
> I think it would be best to list the technical limitations, from the
> kernel's perspective, of the unsupported exception levels and the
> advantages of the supported exception levels here. If you want to guide
> system builders towards EL2, I think it'd be more convincing to document
> the relevant technical aspects (perhaps KVM needs facilities only
> available in EL2) than just providing an unexplained requirement.

That's not meant to be an official document for SoC designers. It just
states the requirements from the Linux kernel perspective. But ARM is
producing platform design documents covering hardware and firmware
requirements and these will be made available.

In short, AArch64 (unlike previously) comes at EL3 out of reset. You
will have firmware running here doing hardware various initialisation
and initialise the secure software if there is one. It then gives
control to the non-secure side (can be UEFI, some boot loader, Linux
etc).

-- 
Catalin
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