Re: [PATCH v3 05/31] arm64: MMU initialisation

[Arnd Bergmann]

On Friday 07 September 2012, Catalin Marinas wrote:
> 
> This patch contains the initialisation of the memory blocks, MMU
> attributes and the memory map. Only five memory types are defined:
> Device nGnRnE (equivalent to Strongly Ordered), Device nGnRE (classic
> Device memory), Device GRE, Normal Non-cacheable and Normal Cacheable.
> Cache policies are supported via the memory attributes register
> (MAIR_EL1) and only affect the Normal Cacheable mappings.
> 
> This patch also adds the SPARSEMEM_VMEMMAP initialisation.
> 
> Signed-off-by: Will Deacon <will.deacon@xxxxxxx>
> Signed-off-by: Catalin Marinas <catalin.marinas@xxxxxxx>
> Acked-by: Tony Lindgren <tony@xxxxxxxxxxx>

Acked-by: Arnd Bergmann <arnd@xxxxxxxx>
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