diff --git a/drivers/gpu/drm/radeon/atombios_crtc.c b/drivers/gpu/drm/radeon/atombios_crtc.c
index 96184d0..1f7e5fe 100644
--- a/drivers/gpu/drm/radeon/atombios_crtc.c
+++ b/drivers/gpu/drm/radeon/atombios_crtc.c
@@ -1565,6 +1565,10 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
 		    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(test_radeon_crtc->encoder))) {
 			/* check if we are already driving this connector with another crtc */
 			if (test_radeon_crtc->connector == radeon_crtc->connector) {
+				DRM_INFO("crtc %d and crtc %d (0x%x) both driving %s\n",
+					 radeon_crtc->crtc_id, test_radeon_crtc->crtc_id,
+					 test_radeon_crtc->pll_id,
+					 drm_get_connector_name(radeon_crtc->connector));
 				/* if we are, return that pll */
 				if (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)
 					return test_radeon_crtc->pll_id;
@@ -1574,8 +1578,10 @@ static int radeon_get_shared_nondp_ppll(struct drm_crtc *crtc)
 			if ((crtc->mode.clock == test_crtc->mode.clock) &&
 			    (adjusted_clock == test_adjusted_clock) &&
 			    (radeon_crtc->ss_enabled == test_radeon_crtc->ss_enabled) &&
-			    (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID))
+			    (test_radeon_crtc->pll_id != ATOM_PPLL_INVALID)) {
+				DRM_INFO("found pll 0x%x with matched clock\n", test_radeon_crtc->pll_id);
 				return test_radeon_crtc->pll_id;
+			}
 		}
 	}
 	return ATOM_PPLL_INVALID;
@@ -1631,6 +1637,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 			/* UNIPHY A uses PPLL2 */
 			return ATOM_PPLL2;
 		else if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+			DRM_INFO("crtc %d is DP\n", radeon_crtc->crtc_id);
 			/* UNIPHY B/C/D/E/F */
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
@@ -1642,6 +1649,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 					return pll;
 			}
 		} else {
+			DRM_INFO("crtc %d is not DP\n", radeon_crtc->crtc_id);
 			/* use the same PPLL for all monitors with the same clock */
 			pll = radeon_get_shared_nondp_ppll(crtc);
 			if (pll != ATOM_PPLL_INVALID)
@@ -1649,6 +1657,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 		}
 		/* UNIPHY B/C/D/E/F */
 		pll_in_use = radeon_get_pll_use_mask(crtc);
+		DRM_INFO("plls in use 0x%x\n", pll_in_use);
 		if (!(pll_in_use & (1 << ATOM_PPLL0)))
 			return ATOM_PPLL0;
 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
@@ -1667,6 +1676,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 		 * crtc virtual pixel clock.
 		 */
 		if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+			DRM_INFO("crtc %d is DP\n", radeon_crtc->crtc_id);
 			if (rdev->clock.dp_extclk)
 				/* skip PPLL programming if using ext clock */
 				return ATOM_PPLL_INVALID;
@@ -1683,6 +1693,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 					return pll;
 			}
 		} else {
+			DRM_INFO("crtc %d is not DP\n", radeon_crtc->crtc_id);
 			/* use the same PPLL for all monitors with the same clock */
 			pll = radeon_get_shared_nondp_ppll(crtc);
 			if (pll != ATOM_PPLL_INVALID)
@@ -1690,6 +1701,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 		}
 		/* all other cases */
 		pll_in_use = radeon_get_pll_use_mask(crtc);
+		DRM_INFO("plls in use 0x%x\n", pll_in_use);
 		if (!(pll_in_use & (1 << ATOM_PPLL2)))
 			return ATOM_PPLL2;
 		if (!(pll_in_use & (1 << ATOM_PPLL1)))
@@ -1703,11 +1715,13 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 			 * DCE3: PPLL1 or PPLL2
 			 */
 			if (ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder))) {
+				DRM_INFO("crtc %d is DP\n", radeon_crtc->crtc_id);
 				/* use the same PPLL for all DP monitors */
 				pll = radeon_get_shared_dp_ppll(crtc);
 				if (pll != ATOM_PPLL_INVALID)
 					return pll;
 			} else {
+				DRM_INFO("crtc %d is not DP\n", radeon_crtc->crtc_id);
 				/* use the same PPLL for all monitors with the same clock */
 				pll = radeon_get_shared_nondp_ppll(crtc);
 				if (pll != ATOM_PPLL_INVALID)
@@ -1715,6 +1729,7 @@ static int radeon_atom_pick_pll(struct drm_crtc *crtc)
 			}
 			/* all other cases */
 			pll_in_use = radeon_get_pll_use_mask(crtc);
+			DRM_INFO("plls in use 0x%x\n", pll_in_use);
 			if (!(pll_in_use & (1 << ATOM_PPLL2)))
 				return ATOM_PPLL2;
 			if (!(pll_in_use & (1 << ATOM_PPLL1)))
@@ -1811,7 +1826,11 @@ static bool atombios_crtc_mode_fixup(struct drm_crtc *crtc,
 	if (!atombios_crtc_prepare_pll(crtc, adjusted_mode))
 		return false;
 	/* pick pll */
+	DRM_INFO("== start crtc %d driving %s ==\n", radeon_crtc->crtc_id,
+		 drm_get_connector_name(radeon_crtc->connector));
 	radeon_crtc->pll_id = radeon_atom_pick_pll(crtc);
+	DRM_INFO("crtc %d using pll 0x%x\n", radeon_crtc->crtc_id, radeon_crtc->pll_id);
+	DRM_INFO("== end crtc %d ==\n", radeon_crtc->crtc_id);
 	/* if we can't get a PPLL for a non-DP encoder, fail */
 	if ((radeon_crtc->pll_id == ATOM_PPLL_INVALID) &&
 	    !ENCODER_MODE_IS_DP(atombios_get_encoder_mode(radeon_crtc->encoder)))