Re: [PATCH 02/31] perf, x86: Basic Haswell PMU support

[Peter Zijlstra]

On Thu, 2012-09-27 at 21:31 -0700, Andi Kleen wrote:
>  /*
> + * Also filter out TSX bits.
> + */
> +#define TSX_FIXED_EVENT_CONSTRAINT(c, n)       \
> +       EVENT_CONSTRAINT(c, (1ULL << (32+n)),   \
> +                        X86_RAW_EVENT_MASK|HSW_INTX|HSW_INTX_CHECKPOINTED)

How volatile are those bits? Will the re-appear in future chips or are
they prone to get re-assigned different semantics in future chips?

If they're 'stable' we might as well add then to FIXED_EVENT_CONSTRAINT,
its not like those bits would ever appear on previous hardware.
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