Re: [RFC] x86: mtrr: Constrain WB MTRR to max phys mem prior to cleanup

[H. Peter Anvin]

On 09/29/2012 01:11 PM, Henrique de Moraes Holschuh wrote:
> On Sat, 29 Sep 2012, H. Peter Anvin wrote:
> > PAT support are lacking only in the Pentium Pro and Pentium II.  Sorry, if
> > you're using crap that old, you don't get to screw up the kernel for
> > everyone else.
>
> PAT is blacklisted for x86_model < 15 on Intel, which covers a lot
> more boxes than p-pro and pII.  There is a comment on kernel/cpu/intel.c:
>
>          /*
>           * There is a known erratum on Pentium III and Core Solo
>           * and Core Duo CPUs.
>           * " Page with PAT set to WC while associated MTRR is UC
>           *   may consolidate to UC "
>           * Because of this erratum, it is better to stick with
>           * setting WC in MTRR rather than using PAT on these CPUs.
>           *
>           * Enable PAT WC only on P4, Core 2 or later CPUs.
>           */
>          if (c->x86 == 6 && c->x86_model < 15)
>                  clear_cpu_cap(c, X86_FEATURE_PAT);
>
> Intel doesn't make it easy to get all processor specification updates at
> once so that I could hunt down every processor which acknowledges the
> existence of that errata before replying, so I will assume for the moment
> that the comment is mostly correct.

Last I checked it was questionable if the erratum actually mattered 
enough to bother with.  What is even more questionable is the number of 
machines which need the workaround *and* need the "MTRR cleanup" mess.

	-hpa

--
H. Peter Anvin, Intel Open Source Technology Center
I work for Intel.  I don't speak on their behalf.

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