This makes the cpu mode of the driver available outside of an FSL SOC
and even powerpc environment. This is accomplished by putting things
regarding fsl specific code and to cpm specific code within ifdefs.
Furthermore, this adds support for the mostly register-compatible
SPICTRL core from the GRLIB VHDL IP core library normally running on
sparc. A different entry in of_fsl_spi_match matches this core and
indicates a different hardware type that is used to set up different
function pointers and special cases. The fetching of irq is changed to
work under sparc as well.
The GRLIB core operates in cpu mode and from the driver's point of view
the important differences are that the number of bits per word might be
limited and that there might be native chipselects selected via the
added slvsel register. These differences if present are indicated by an
added capabilities register.
Signed-off-by: Andreas Larsson <andreas@xxxxxxxxxxx>