[PATCH] tidspbridge: Fix compilation

[Pali RohÃr]

Fix includes and use clk_prepare_enable/clk_disable_unprepare

Signed-off-by: Pali RohÃr <pali.rohar@xxxxxxxxx>
Signed-off-by: Joni Lapilainen <joni.lapilainen@xxxxxxxxx>
---
 drivers/staging/tidspbridge/core/dsp-clock.c  |   16 ++++++++--------
 drivers/staging/tidspbridge/core/tiomap3430.c |    2 ++
 drivers/staging/tidspbridge/core/tiomap_io.c  |    2 ++
 drivers/staging/tidspbridge/core/wdt.c        |    8 ++++----
 4 files changed, 16 insertions(+), 12 deletions(-)

diff --git a/drivers/staging/tidspbridge/core/dsp-clock.c b/drivers/staging/tidspbridge/core/dsp-clock.c
index 2f084e18..7d56693 100644
--- a/drivers/staging/tidspbridge/core/dsp-clock.c
+++ b/drivers/staging/tidspbridge/core/dsp-clock.c
@@ -221,7 +221,7 @@ int dsp_clk_enable(enum dsp_clk_id clk_id)
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
-		clk_enable(iva2_clk);
+		clk_prepare_enable(iva2_clk);
 		break;
 	case GPT_CLK:
 		status = omap_dm_timer_start(timer[clk_id - 1]);
@@ -236,9 +236,9 @@ int dsp_clk_enable(enum dsp_clk_id clk_id)
 		dev_err(bridge, "ERROR: DSP requested to enable WDT3 clk\n");
 		break;
 	case SSI_CLK:
-		clk_enable(ssi.sst_fck);
-		clk_enable(ssi.ssr_fck);
-		clk_enable(ssi.ick);
+		clk_prepare_enable(ssi.sst_fck);
+		clk_prepare_enable(ssi.ssr_fck);
+		clk_prepare_enable(ssi.ick);
 
 		/*
 		 * The SSI module need to configured not to have the Forced
@@ -297,7 +297,7 @@ int dsp_clk_disable(enum dsp_clk_id clk_id)
 
 	switch (get_clk_type(clk_id)) {
 	case IVA2_CLK:
-		clk_disable(iva2_clk);
+		clk_disable_unprepare(iva2_clk);
 		break;
 	case GPT_CLK:
 		status = omap_dm_timer_stop(timer[clk_id - 1]);
@@ -314,9 +314,9 @@ int dsp_clk_disable(enum dsp_clk_id clk_id)
 	case SSI_CLK:
 		ssi_clk_prepare(false);
 		ssi_clk_prepare(false);
-		clk_disable(ssi.sst_fck);
-		clk_disable(ssi.ssr_fck);
-		clk_disable(ssi.ick);
+		clk_disable_unprepare(ssi.sst_fck);
+		clk_disable_unprepare(ssi.ssr_fck);
+		clk_disable_unprepare(ssi.ick);
 		break;
 	default:
 		dev_err(bridge, "Invalid clock id for disable\n");
diff --git a/drivers/staging/tidspbridge/core/tiomap3430.c b/drivers/staging/tidspbridge/core/tiomap3430.c
index f619fb3..1ba45b1 100644
--- a/drivers/staging/tidspbridge/core/tiomap3430.c
+++ b/drivers/staging/tidspbridge/core/tiomap3430.c
@@ -55,6 +55,8 @@
 #include "_tiomap_pwr.h"
 #include "tiomap_io.h"
 
+#include "../../../../arch/arm/mach-omap2/cm3xxx.h"
+
 /* Offset in shared mem to write to in order to synchronize start with DSP */
 #define SHMSYNCOFFSET 4		/* GPP byte offset */
 
diff --git a/drivers/staging/tidspbridge/core/tiomap_io.c b/drivers/staging/tidspbridge/core/tiomap_io.c
index f53ed98..b481bd8 100644
--- a/drivers/staging/tidspbridge/core/tiomap_io.c
+++ b/drivers/staging/tidspbridge/core/tiomap_io.c
@@ -33,6 +33,8 @@
 #include "_tiomap_pwr.h"
 #include "tiomap_io.h"
 
+#include "../../../../arch/arm/mach-omap2/cm3xxx.h"
+
 static u32 ul_ext_base;
 static u32 ul_ext_end;
 
diff --git a/drivers/staging/tidspbridge/core/wdt.c b/drivers/staging/tidspbridge/core/wdt.c
index 7ff0e6c..b7f2348 100644
--- a/drivers/staging/tidspbridge/core/wdt.c
+++ b/drivers/staging/tidspbridge/core/wdt.c
@@ -128,8 +128,8 @@ void dsp_wdt_enable(bool enable)
 	wdt_enable = enable;
 
 	if (enable) {
-		clk_enable(dsp_wdt.fclk);
-		clk_enable(dsp_wdt.iclk);
+		clk_prepare_enable(dsp_wdt.fclk);
+		clk_prepare_enable(dsp_wdt.iclk);
 		dsp_wdt.sm_wdt->wdt_setclocks = 1;
 		tmp = __raw_readl(dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
 		__raw_writel(tmp, dsp_wdt.reg_base + OMAP3_WDT3_ISR_OFFSET);
@@ -137,7 +137,7 @@ void dsp_wdt_enable(bool enable)
 	} else {
 		disable_irq(INT_34XX_WDT3_IRQ);
 		dsp_wdt.sm_wdt->wdt_setclocks = 0;
-		clk_disable(dsp_wdt.iclk);
-		clk_disable(dsp_wdt.fclk);
+		clk_disable_unprepare(dsp_wdt.iclk);
+		clk_disable_unprepare(dsp_wdt.fclk);
 	}
 }
-- 
1.7.10.4

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