Re: [Intel-gfx] [git pull] drm merge for 3.9-rc1

From: Sedat Dilek
Date: Thu Feb 28 2013 - 12:59:22 EST

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In reply to: Paulo Zanoni: "Re: [Intel-gfx] [git pull] drm merge for 3.9-rc1"
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On Thu, Feb 28, 2013 at 6:33 PM, Paulo Zanoni <przanoni@xxxxxxxxx> wrote:
> Hi
>
> 2013/2/28 Sedat Dilek <sedat.dilek@xxxxxxxxx>:
>> On Thu, Feb 28, 2013 at 6:12 PM, Sedat Dilek <sedat.dilek@xxxxxxxxx> wrote:
>>> On Thu, Feb 28, 2013 at 3:31 PM, Paulo Zanoni <przanoni@xxxxxxxxx> wrote:
>>>> Hi
>>>>
>>>> 2013/2/28 Chris Wilson <chris@xxxxxxxxxxxxxxxxxx>:
>>>>> On Thu, Feb 28, 2013 at 12:06:28AM +0100, Sedat Dilek wrote:
>>>>>> On Wed, Feb 27, 2013 at 11:36 PM, Sedat Dilek <sedat.dilek@xxxxxxxxx> wrote:
>>>>>> > Hi,
>>>>>> >
>>>>>> > I am seeing this also on Linux-Next.
>>>>>> >
>>>>>> > /var/log/kern.log:Feb 27 22:52:35 fambox kernel: [ 28.202381]
>>>>>> > [drm:intel_dp_aux_wait_done] *ERROR* dp aux hw did not signal timeout
>>>>>> > (has irq: 1)!
>>>>>> > /var/log/kern.log:Feb 27 22:52:35 fambox kernel: [ 28.210588]
>>>>>> > [drm:intel_dp_aux_wait_done] *ERROR* dp aux hw did not signal timeout
>>>>>> > (has irq: 1)!
>>>>>> >
>>>>>> > /var/log/kern.log.1:Feb 22 07:36:04 fambox kernel: [ 27.408280]
>>>>>> > [drm:intel_dp_aux_wait_done] *ERROR* dp aux hw did not signal timeout
>>>>>> > (has irq: 1)!
>>>>>> >
>>>>>> > This seems to be hard reproducible...
>>>>>> > Laptop-LCD... Sandybridge Mobile-GT2.
>>>>>> >
>>>>>> > Is there a way to force the error?
>>>>>> >
>>>>>> > Possible patch see [1].
>>>>>> >
>>>>>> > - Sedat -
>>>>>> >
>>>>>> > [1] https://patchwork.kernel.org/patch/2192721/
>>>>>
>>>>> That was:
>>>>>
>>>>> + if (!done) {
>>>>> + status = I915_READ_NOTRACE(ch_ctl);
>>>>> + DRM_ERROR("dp aux hw did not signal timeout (has irq:
>>>>> %i), status=%08x!\n",
>>>>> + has_aux_irq, status);
>>>>> + }
>>>>>
>>>>> You applied
>>>>>
>>>>> + if (!done) {
>>>>> + status = I915_READ_NOTRACE(ch_ctl);
>>>>> + DRM_ERROR("dp aux hw did not signal timeout (has irq:
>>>>> %i), status=%08x!\n",
>>>>> + has_aux_irq, status);
>>>>> + {
>>>>
>>>> In addition to this, after the problem happens can you please dump the
>>>> registers 0x44008 (DEIIR) and 0xC4008 (SDEIIR)? You can do this either
>>>> by running intel-reg-read (from intel-gpu-tools) or by changing the
>>>> DRM_ERROR above to also print the result of I915_READ(0x44008) and
>>>> I915_READ(0xC4008).
>>>>
>>>
>>> Do I need a specific version of intel-gpu-tools?
>>> Ubuntu/precise has v1.2 in its archives - sufficient?
>>> Note: The error was twice after dozenz of Linux-Next kernel builds.
>>>
>>> - Sedat -
>>>
>>> [1] http://packages.ubuntu.com/precise/intel-gpu-tools
>>>
>>
>> Installed intel-gpu-tools.
>>
>> # intel_reg_read
>> Usage: intel_reg_read [-f | addr]
>> -f : read back full range of registers.
>> WARNING! This could be danger to hang the machine!
>> addr : in 0xXXXX format
>>
>> # intel_reg_read 0x44008
>> Couldn't map MMIO region: Resource temporarily unavailable
>>
>> [ 368.281707] intel_reg_read:3657 conflicting memory types
>> f0000000-f0400000 uncached-minus<->write-combining
>> [ 381.521912] intel_reg_read:3658 conflicting memory types
>> f0000000-f0400000 uncached-minus<->write-combining
>> [ 401.136291] intel_reg_read:3659 conflicting memory types
>> f0000000-f0400000 uncached-minus<->write-combining
>>
>> Wrong i-g-t version? Missing enabled kernel-config option? Boot with
>> i915 debug enabled?
>
> Just build the version from git and it should work
> (http://cgit.freedesktop.org/xorg/app/intel-gpu-tools/).
>

NO.

$ git clone git://anongit.freedesktop.org/xorg/app/intel-gpu-tools
intel-gpu-tools-git

$ cd intel-gpu-tools-git/

$ ./autogen.sh --disable-dumper <--- requires swig2.0 and python >=3.x

$ sudo ./tools/intel_reg_read 0x44008
0x44008 : 0x0

$ sudo ./tools/intel_reg_read 0xC4008
0xC4008 : 0x0

$ sudo ./tools/intel_reg_dumper > /tmp/intel_reg_dumper.txt <--- see attachment

Does this help you?

- Sedat -

>>
>> - Sedat -
>>
>>>> If you conclude that the value of 0x44008 is 0x0 while the value of
>>>> 0xC4008 is not, then this patch should help:
>>>> https://patchwork.kernel.org/patch/2177841/
>>>>
>>>>>
>>>>> That second '{' is the source of the compile error.
>>>>> -Chris
>>>>>
>>>>> --
>>>>> Chris Wilson, Intel Open Source Technology Centre
>>>>> _______________________________________________
>>>>> Intel-gfx mailing list
>>>>> Intel-gfx@xxxxxxxxxxxxxxxxxxxxx
>>>>> http://lists.freedesktop.org/mailman/listinfo/intel-gfx
>>>>
>>>>
>>>>
>>>> --
>>>> Paulo Zanoni
>
>
>
> --
> Paulo Zanoni
PGETBL_CTL: 0x00000000
GEN6_INSTDONE_1: 0xfffffffe
GEN6_INSTDONE_2: 0xffffffff
CPU_VGACNTRL: 0x80000000 (disabled)
DIGITAL_PORT_HOTPLUG_CNTRL: 0x00000000
RR_HW_CTL: 0x00000000 (low 0, high 0)
FDI_PLL_BIOS_0: 0xffffffff
FDI_PLL_BIOS_1: 0xffffffff
FDI_PLL_BIOS_2: 0xffffffff
DISPLAY_PORT_PLL_BIOS_0: 0xffffffff
DISPLAY_PORT_PLL_BIOS_1: 0xffffffff
DISPLAY_PORT_PLL_BIOS_2: 0xffffffff
FDI_PLL_FREQ_CTL: 0xffffffff
PIPEACONF: 0xc0000010 (enabled, active, pf-pd, rotate 0, 8bpc)
HTOTAL_A: 0x05cd0555 (1366 active, 1486 total)
HBLANK_A: 0x05cd0555 (1366 start, 1486 end)
HSYNC_A: 0x05a50585 (1414 start, 1446 end)
VTOTAL_A: 0x031702ff (768 active, 792 total)
VBLANK_A: 0x031702ff (768 start, 792 end)
VSYNC_A: 0x03060301 (770 start, 775 end)
VSYNCSHIFT_A: 0x00000000
PIPEASRC: 0x055502ff (1366, 768)
PIPEA_DATA_M1: 0x7e19e420 (TU 64, val 0x19e420 1696800)
PIPEA_DATA_N1: 0x0020f580 (val 0x20f580 2160000)
PIPEA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEA_DATA_N2: 0x00000000 (val 0x0 0)
PIPEA_LINK_M1: 0x0001142c (val 0x1142c 70700)
PIPEA_LINK_N1: 0x00041eb0 (val 0x41eb0 270000)
PIPEA_LINK_M2: 0x00000000 (val 0x0 0)
PIPEA_LINK_N2: 0x00000000 (val 0x0 0)
DSPACNTR: 0xd8004400 (enabled)
DSPABASE: 0x00000000
DSPASTRIDE: 0x00001600 (88)
DSPASURF: 0x0047a000
DSPATILEOFF: 0x00000000 (0, 0)
PIPEBCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
HTOTAL_B: 0x00000000 (1 active, 1 total)
HBLANK_B: 0x00000000 (1 start, 1 end)
HSYNC_B: 0x00000000 (1 start, 1 end)
VTOTAL_B: 0x00000000 (1 active, 1 total)
VBLANK_B: 0x00000000 (1 start, 1 end)
VSYNC_B: 0x00000000 (1 start, 1 end)
VSYNCSHIFT_B: 0x00000000
PIPEBSRC: 0x00000000 (1, 1)
PIPEB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N1: 0x00000000 (val 0x0 0)
PIPEB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEB_DATA_N2: 0x00000000 (val 0x0 0)
PIPEB_LINK_M1: 0x00000000 (val 0x0 0)
PIPEB_LINK_N1: 0x00000000 (val 0x0 0)
PIPEB_LINK_M2: 0x00000000 (val 0x0 0)
PIPEB_LINK_N2: 0x00000000 (val 0x0 0)
DSPBCNTR: 0x00004000 (disabled)
DSPBBASE: 0x00000000
DSPBSTRIDE: 0x00000000 (0)
DSPBSURF: 0x00000000
DSPBTILEOFF: 0x00000000 (0, 0)
PIPECCONF: 0x00000000 (disabled, inactive, pf-pd, rotate 0, 8bpc)
HTOTAL_C: 0x00000000 (1 active, 1 total)
HBLANK_C: 0x00000000 (1 start, 1 end)
HSYNC_C: 0x00000000 (1 start, 1 end)
VTOTAL_C: 0x00000000 (1 active, 1 total)
VBLANK_C: 0x00000000 (1 start, 1 end)
VSYNC_C: 0x00000000 (1 start, 1 end)
VSYNCSHIFT_C: 0x00000000
PIPECSRC: 0x00000000 (1, 1)
PIPEC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
PIPEC_DATA_N1: 0x00000000 (val 0x0 0)
PIPEC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
PIPEC_DATA_N2: 0x00000000 (val 0x0 0)
PIPEC_LINK_M1: 0x00000000 (val 0x0 0)
PIPEC_LINK_N1: 0x00000000 (val 0x0 0)
PIPEC_LINK_M2: 0x00000000 (val 0x0 0)
PIPEC_LINK_N2: 0x00000000 (val 0x0 0)
DSPCCNTR: 0x00000000 (disabled)
DSPCBASE: 0x00000000
DSPCSTRIDE: 0x00000000 (0)
DSPCSURF: 0x00000000
DSPCTILEOFF: 0x00000000 (0, 0)
PFA_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFA_CTL_2: 0x00007e80 (vscale 0.988281)
PFA_CTL_3: 0x00003f40 (vscale initial phase 0.494141)
PFA_CTL_4: 0x00007d54 (hscale 0.979126)
PFA_WIN_POS: 0x00000000 (0, 0)
PFA_WIN_SIZE: 0x00000000 (0, 0)
PFB_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFB_CTL_2: 0x00000000 (vscale 0.000000)
PFB_CTL_3: 0x00000000 (vscale initial phase 0.000000)
PFB_CTL_4: 0x00000000 (hscale 0.000000)
PFB_WIN_POS: 0x00000000 (0, 0)
PFB_WIN_SIZE: 0x00000000 (0, 0)
PFC_CTL_1: 0x00000000 (disable, auto_scale yes, auto_scale_cal no, v_filter enable, vadapt disable, mode least, filter_sel programmed,chroma pre-filter disable, vert3tap auto, v_inter_invert field 1)
PFC_CTL_2: 0x00000000 (vscale 0.000000)
PFC_CTL_3: 0x00000000 (vscale initial phase 0.000000)
PFC_CTL_4: 0x00000000 (hscale 0.000000)
PFC_WIN_POS: 0x00000000 (0, 0)
PFC_WIN_SIZE: 0x00000000 (0, 0)
PCH_DREF_CONTROL: 0x00001402 (cpu source disable, ssc_source enable, nonspread_source enable, superspread_source disable, ssc4_mode downspread, ssc1 enable, ssc4 disable)
PCH_RAWCLK_FREQ: 0x0000007d (FDL_TP1 timer 0.5us, FDL_TP2 timer 1.5us, freq 125)
PCH_DPLL_TMR_CFG: 0x0271186a
PCH_SSC4_PARMS: 0x01204860
PCH_SSC4_AUX_PARMS: 0x000029c5
PCH_DPLL_SEL: 0x00000008 (TransA DPLL enable (DPLL A), TransB DPLL disable (DPLL (null)))
PCH_DPLL_ANALOG_CTL: 0x00008000
PCH_DPLL_A: 0x88046004 (enable, sdvo high speed no, mode LVDS, p2 Div 14, FPA0 P1 3, FPA1 P1 3, refclk SSC, sdvo/hdmi mul 1)
PCH_DPLL_B: 0x04800080 (disable, sdvo high speed no, mode (null), p2 (null), FPA0 P1 8, FPA1 P1 8, refclk default 120Mhz, sdvo/hdmi mul 1)
PCH_FPA0: 0x00021007 (n = 2, m1 = 16, m2 = 7)
PCH_FPA1: 0x00021007 (n = 2, m1 = 16, m2 = 7)
PCH_FPB0: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
PCH_FPB1: 0x00030d07 (n = 3, m1 = 13, m2 = 7)
TRANS_HTOTAL_A: 0x05cd0555 (1366 active, 1486 total)
TRANS_HBLANK_A: 0x05cd0555 (1366 start, 1486 end)
TRANS_HSYNC_A: 0x05a50585 (1414 start, 1446 end)
TRANS_VTOTAL_A: 0x031702ff (768 active, 792 total)
TRANS_VBLANK_A: 0x031702ff (768 start, 792 end)
TRANS_VSYNC_A: 0x03060301 (770 start, 775 end)
TRANS_VSYNCSHIFT_A: 0x00000000
TRANSA_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N1: 0x00000000 (val 0x0 0)
TRANSA_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSA_DATA_N2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSA_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_B: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_B: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_B: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_B: 0x00000000 (1 start, 1 end)
TRANS_VSYNCSHIFT_B: 0x00000000
TRANSB_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N1: 0x00000000 (val 0x0 0)
TRANSB_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSB_DATA_N2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSB_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANS_HTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_HBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_HSYNC_C: 0x00000000 (1 start, 1 end)
TRANS_VTOTAL_C: 0x00000000 (1 active, 1 total)
TRANS_VBLANK_C: 0x00000000 (1 start, 1 end)
TRANS_VSYNC_C: 0x00000000 (1 start, 1 end)
TRANS_VSYNCSHIFT_C: 0x00000000
TRANSC_DATA_M1: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N1: 0x00000000 (val 0x0 0)
TRANSC_DATA_M2: 0x00000000 (TU 1, val 0x0 0)
TRANSC_DATA_N2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N1: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_M2: 0x00000000 (val 0x0 0)
TRANSC_DP_LINK_N2: 0x00000000 (val 0x0 0)
TRANSACONF: 0xc0000000 (enable, active, progressive)
TRANSBCONF: 0x00000000 (disable, inactive, progressive)
TRANSCCONF: 0x00000000 (disable, inactive, progressive)
FDI_TXA_CTL: 0xb0044000 (enable, train pattern not train, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL enable, scrambing enable, master mode disable)
FDI_TXB_CTL: 0x00040000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing enable, FDI PLL disable, scrambing enable, master mode disable)
FDI_TXC_CTL: 0x00000000 (disable, train pattern pattern_1, voltage swing 0.4V,pre-emphasis 0dB, port width X1, enhanced framing disable, FDI PLL disable, scrambing enable, master mode disable)
FDI_RXA_CTL: 0x80002350 (enable, train pattern not train, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL enable,FS ecc disable, FE ecc disable, FS err report enable, FE err report enable,scrambing enable, enhanced framing enable, PCDClk)
FDI_RXB_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
FDI_RXC_CTL: 0x00000040 (disable, train pattern pattern_1, port width X1, 8bpc,link_reverse_strap_overwrite no, dmi_link_reverse no, FDI PLL disable,FS ecc disable, FE ecc disable, FS err report disable, FE err report disable,scrambing enable, enhanced framing enable, RawClk)
DPAFE_BMFUNC: 0x8e97861c
DPAFE_DL_IREFCAL0: 0x00000b6d
DPAFE_DL_IREFCAL1: 0x00000b6d
DPAFE_DP_IREFCAL: 0x00000965
PCH_DSPCLK_GATE_D: 0x100000a0
PCH_DSP_CHICKEN1: 0x00600000
PCH_DSP_CHICKEN2: 0x0260c000
PCH_DSP_CHICKEN3: 0x00000000
FDI_RXA_MISC: 0x00200090 (FDI Delay 144)
FDI_RXB_MISC: 0x00000080 (FDI Delay 128)
FDI_RXC_MISC: 0x00000080 (FDI Delay 128)
FDI_RXA_TUSIZE1: 0x7e000000
FDI_RXA_TUSIZE2: 0x7e000000
FDI_RXB_TUSIZE1: 0x7e000000
FDI_RXB_TUSIZE2: 0x7e000000
FDI_RXC_TUSIZE1: 0x7e000000
FDI_RXC_TUSIZE2: 0x7e000000
FDI_PLL_CTL_1: 0x7e000000
FDI_PLL_CTL_2: 0x7e000000
FDI_RXA_IIR: 0x00000000
FDI_RXA_IMR: 0x000008ff
FDI_RXB_IIR: 0x00000000
FDI_RXB_IMR: 0x000008ff
PCH_ADPA: 0x00f40000 (disabled, transcoder A, -hsync, -vsync)
HDMIB: 0x0000001c (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync detected)
HDMIC: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
HDMID: 0x00000018 (disabled pipe A 8bpc SDVO DVI audio disabled +vsync +hsync non-detected)
PCH_LVDS: 0x813003c2 (enabled, pipe A, 24 bit, 1 channel)
CPU_eDP_A: 0x00000018
PCH_DP_B: 0x00000004
PCH_DP_C: 0x00000000
PCH_DP_D: 0x00000000
TRANS_DP_CTL_A: 0x60000018 (disable port none 8bpc +vsync +hsync)
TRANS_DP_CTL_B: 0x60000018 (disable port none 8bpc +vsync +hsync)
TRANS_DP_CTL_C: 0x60000018 (disable port none 8bpc +vsync +hsync)
BLC_PWM_CPU_CTL2: 0x80000000
BLC_PWM_CPU_CTL: 0x000003fc
BLC_PWM_PCH_CTL1: 0x80000000
BLC_PWM_PCH_CTL2: 0x12281228
PCH_PP_STATUS: 0xc0000008 (on, ready, sequencing idle)
PCH_PP_CONTROL: 0xabcd0003 (blacklight disabled, power down on reset, panel on)
PCH_PP_ON_DELAYS: 0x01901388
PCH_PP_OFF_DELAYS: 0x012c1388
PCH_PP_DIVISOR: 0x00186905
PORT_DBG: 0x00000000 (HW DRRS off)
RC6_RESIDENCY_TIME: 0x6858843c
RC6p_RESIDENCY_TIME: 0x00000000
RC6pp_RESIDENCY_TIME: 0x00000000
GEN6_RP_CONTROL: 0x00000d91 (enabled)
GEN6_RPNSWREQ: 0x0e000000
GEN6_RP_DOWN_TIMEOUT: 0x000f4240
GEN6_RP_INTERRUPT_LIMITS: 0x17070000
GEN6_RP_UP_THRESHOLD: 0x0000e808
GEN6_RP_UP_EI: 0x000101d0
GEN6_RP_DOWN_EI: 0x00055730
GEN6_RP_IDLE_HYSTERSIS: 0x0000000a
GEN6_RC_STATE: 0x00000000
GEN6_RC_CONTROL: 0x88040000
GEN6_RC1_WAKE_RATE_LIMIT: 0x03e80000
GEN6_RC6_WAKE_RATE_LIMIT: 0x0028001e
GEN6_RC_EVALUATION_INTERVAL: 0x0001e848
GEN6_RC_IDLE_HYSTERSIS: 0x00000019
GEN6_RC_SLEEP: 0x00000000
GEN6_RC1e_THRESHOLD: 0x000003e8
GEN6_RC6_THRESHOLD: 0x0000c350
GEN6_RC_VIDEO_FREQ: 0x18000000
GEN6_PMIER: 0x00000070
GEN6_PMIMR: 0x00000000
GEN6_PMINTRMSK: 0x00000000

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