Re: [PATCH RESEND 0/3] perf, amd: Support for Family 16h L2IPerformance Counters

[Stephane Eranian]

On Wed, Apr 10, 2013 at 1:49 PM, Peter Zijlstra <a.p.zijlstra@xxxxxxxxx> wrote:
> On Wed, 2013-04-10 at 13:38 +0200, Stephane Eranian wrote:
>> On Wed, Apr 10, 2013 at 11:41 AM, Peter Zijlstra <a.p.zijlstra@xxxxxxxxx> wrote:
>> >
>> > On Tue, 2013-04-09 at 10:23 -0500, Jacob Shin wrote:
>> > > Upcoming AMD Family 16h Processors provide 4 new performance counters
>> > > to count L2 related events. Similar to northbridge counters, these new
>> > > counters are shared across multiple CPUs that share the same L2 cache.
>> > > This patchset adds support for these new counters and enforces sharing
>> > > by leveraging the existing sharing logic used for the northbridge
>> > > counters.
>> >
>> > If they're separate counters -- not shared with the regular cpu
>> > counters like the 10h NB counters are, then they should have their own
>> > PMU driver.
>> >
>> > Similar to the 15h NB counters; which are a separate set of counters
>> > and no longer overlay the normal counters.
>> >
>> Well, that's how this was suggested but that's not how it's
>> implemented currently
>> and committed if I recall.
>
> Hmm.. the 15h old interface bits got merged? I thought I kept telling
> that should be done like the intel uncore stuff since the hardware
> interface wasn't retarded anymore.
>
I remember. I agreed with you on this. I don't recall the details as to
why Robert did not like that but I think it had to do with code duplication
from the perf_event_amd.c.
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