Re: [PATCH v2 13/15] powerpc/85xx: add support for e6500 L1 cacheoperation

[Zhao Chenhui]

On Tue, Apr 23, 2013 at 07:00:49PM -0500, Scott Wood wrote:
> On 04/19/2013 05:47:46 AM, Zhao Chenhui wrote:
> >From: Chen-Hui Zhao <chenhui.zhao@xxxxxxxxxxxxx>
> >
> >The L1 Data Cache of e6500 contains no modified data, no flush
> >is required.
> >
> >Signed-off-by: Zhao Chenhui <chenhui.zhao@xxxxxxxxxxxxx>
> >Signed-off-by: Li Yang <leoli@xxxxxxxxxxxxx>
> >Signed-off-by: Andy Fleming <afleming@xxxxxxxxxxxxx>
> >---
> > arch/powerpc/kernel/fsl_booke_cache.S |   11 ++++++++++-
> > 1 files changed, 10 insertions(+), 1 deletions(-)
> >
> >diff --git a/arch/powerpc/kernel/fsl_booke_cache.S
> >b/arch/powerpc/kernel/fsl_booke_cache.S
> >index 232c47b..24a52bb 100644
> >--- a/arch/powerpc/kernel/fsl_booke_cache.S
> >+++ b/arch/powerpc/kernel/fsl_booke_cache.S
> >@@ -65,13 +65,22 @@ _GLOBAL(flush_dcache_L1)
> >
> > 	blr
> >
> >+#define PVR_E6500	0x8040
> >+
> > /* Flush L1 d-cache, invalidate and disable d-cache and i-cache */
> > _GLOBAL(__flush_disable_L1)
> >+/* L1 Data Cache of e6500 contains no modified data, no flush is
> >required */
> >+	mfspr	r3, SPRN_PVR
> >+	rlwinm	r4, r3, 16, 0xffff
> >+	lis	r5, 0
> >+	ori	r5, r5, PVR_E6500@l
> >+	cmpw	r4, r5
> >+	beq	2f
> > 	mflr	r10
> > 	bl	flush_dcache_L1	/* Flush L1 d-cache */
> > 	mtlr	r10
> >
> >-	msync
> >+2:	msync
> > 	mfspr	r4, SPRN_L1CSR0	/* Invalidate and disable d-cache */
> > 	li	r5, 2
> > 	rlwimi	r4, r5, 0, 3
> 
> Note that disabling the cache is a core operation, rather than a
> thread operation.  Is this only called when the second thread is
> disabled?
> 
> -Scott

It is called only when a core is down.
I can add a comment in the code.

-Chenhui

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