[PATCH 12/31] MIPS: Add instruction format information for WAIT, MTC0, MFC0, et al.

[David Daney]

From: David Daney <david.daney@xxxxxxxxxx>

---
 arch/mips/include/uapi/asm/inst.h | 23 ++++++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index 0f4aec2..133abc1 100644
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -117,7 +117,8 @@ enum bcop_op {
 enum cop0_coi_func {
 	tlbr_op	      = 0x01, tlbwi_op	    = 0x02,
 	tlbwr_op      = 0x06, tlbp_op	    = 0x08,
-	rfe_op	      = 0x10, eret_op	    = 0x18
+	rfe_op	      = 0x10, eret_op	    = 0x18,
+	wait_op	      = 0x20
 };
 
 /*
@@ -567,6 +568,24 @@ struct b_format {			/* BREAK and SYSCALL */
 	;)))
 };
 
+struct c0_format {			/* WAIT, TLB?? */
+	BITFIELD_FIELD(unsigned int opcode : 6,
+	BITFIELD_FIELD(unsigned int co : 1,
+	BITFIELD_FIELD(unsigned int code : 19,
+	BITFIELD_FIELD(unsigned int func : 6,
+	;))))
+};
+
+struct c0m_format {			/* MTC0, MFC0, ... */
+	BITFIELD_FIELD(unsigned int opcode : 6,
+	BITFIELD_FIELD(unsigned int func : 5,
+	BITFIELD_FIELD(unsigned int rt : 5,
+	BITFIELD_FIELD(unsigned int rd : 5,
+	BITFIELD_FIELD(unsigned int code : 8,
+	BITFIELD_FIELD(unsigned int sel : 3,
+	;))))))
+};
+
 struct ps_format {			/* MIPS-3D / paired single format */
 	BITFIELD_FIELD(unsigned int opcode : 6,
 	BITFIELD_FIELD(unsigned int rs : 5,
@@ -857,6 +876,8 @@ union mips_instruction {
 	struct f_format f_format;
 	struct ma_format ma_format;
 	struct b_format b_format;
+	struct c0_format c0_format;
+	struct c0m_format c0m_format;
 	struct ps_format ps_format;
 	struct v_format v_format;
 	struct fb_format fb_format;
-- 
1.7.11.7

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