Re: [PATCH v2 2/4] dma: move dw_dmac driver to an own directory

[Vinod Koul]

On Wed, Jun 12, 2013 at 12:07:24PM +0300, Andy Shevchenko wrote:
> On Wed, Jun 12, 2013 at 11:19 AM, Vinod Koul <vinod.koul@xxxxxxxxx> wrote:
> > On Wed, Jun 12, 2013 at 02:23:39PM +0530, Viresh Kumar wrote:
> >> On 12 June 2013 13:42, Vinod Koul <vinod.koul@xxxxxxxxx> wrote:
> >>
> >> > Never mind, am applying your patches and below fix, let me if you guys are okay
Also, please ensure you _run_ checkpatch. There were few trvial errors in this.
I have fixed them up before applying

> >> This information was useful to understand this config option and must
> >> be kept in some way.
> > Well now the config option is not selected by users, so they dont need to know.
> > It was useful in knowing what to select earlier
> >
> > For documenting, we can add this in commit log or better in driver code where
> > you use this
> 
> The driver is better place if you decide to move it (drivers/dma/dw/regs.h).
Okay here it is:


diff --git a/drivers/dma/dw/Kconfig b/drivers/dma/dw/Kconfig
index db2b41f..7be1cf8 100644
--- a/drivers/dma/dw/Kconfig
+++ b/drivers/dma/dw/Kconfig
@@ -10,6 +10,7 @@ config DW_DMAC_CORE
 config DW_DMAC
 	tristate "Synopsys DesignWare AHB DMA platform driver"
 	select DW_DMAC_CORE
+	select DW_DMAC_BIG_ENDIAN_IO if ARCH=AVR32
 	default y if CPU_AT32AP7000
 	help
 	  Support the Synopsys DesignWare AHB DMA controller. This
@@ -25,12 +26,4 @@ config DW_DMAC_PCI
 	  Intel Medfield has integrated this GPDMA controller.
 
 config DW_DMAC_BIG_ENDIAN_IO
-	bool "Use big endian I/O register access"
-	default y if AVR32
-	depends on DW_DMAC_CORE
-	help
-	  Say yes here to use big endian I/O access when reading and writing
-	  to the DMA controller registers. This is needed on some platforms,
-	  like the Atmel AVR32 architecture.
-
-	  If unsure, use the default setting.
+	bool
diff --git a/drivers/dma/dw/regs.h b/drivers/dma/dw/regs.h
index 07c5a6e..deb4274 100644
--- a/drivers/dma/dw/regs.h
+++ b/drivers/dma/dw/regs.h
@@ -101,6 +101,12 @@ struct dw_dma_regs {
 	u32	DW_PARAMS;
 };
 
+/*
+ * Big endian I/O access when reading and writing to the DMA controller
+ * registers.  This is needed on some platforms, like the Atmel AVR32
+ * architecture.
+ */
+
 #ifdef CONFIG_DW_DMAC_BIG_ENDIAN_IO
 #define dma_readl_native ioread32be
 #define dma_writel_native iowrite32be

--
~Vinod
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